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Fri, 10 Jun 2022 14:55:28 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, bhelgaas@google.com Cc: Hou Zhiqiang Subject: [PATCH] PCI: Align MPS to upstream bridge for SAFE and PERFORMANCE mode Date: Fri, 10 Jun 2022 23:01:31 +0800 Message-Id: <20220610150131.6256-1-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: SI2PR02CA0054.apcprd02.prod.outlook.com (2603:1096:4:196::13) To DB9PR04MB9236.eurprd04.prod.outlook.com (2603:10a6:10:370::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bdf45b7c-9ffd-49bf-98c8-08da4af141d5 X-MS-TrafficTypeDiagnostic: AM0PR04MB5346:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0jJJaaJPCRWej2KPLSgvwDsxSmZaPjetO1z0Sxnzq9g1/IfzzQqfum/DXu1QvGXuHfolqRPSHKnAUYxCqBSX2G5EXEf4jlhg0PcCwY50UxKyJcJxTRAUF6wufPUs2fiv9UlXzuXKHggApZiT4BIUp8803h6+HvnD+Bw8q2gdZGhM0yyFwTME/3phoGJ+8Ck7YvW2Z8+1XXLddfvwfNybw+FhGziQVcrZnil6Sld7w6EgbhhNa3QVXfzdRhlwvv3CxlLklu1jEZ9hjLeaAC0zsRW/DOdjBu8iSlD+AohjnTsSrFg3lNYaBwn7NA0McTGQ5nnBs1MQY3wVoPAT/Iflng2HOwNrZaqZJ7AsNTUfDQpi7Q7xA2vG7/QhNglBQPVmIKdXY4fB5Ansxrb0b72I9hdF0NLdXaGGqH84R2JAvbBUQFbrOrpAEvjPuZko2a7ZNQN1s2O7Bo3qdW8b7zb4qFSlx7lLKh03H9R9jhO0CGllvbnS3L9X37R5/hsz60ko+dULVDJCu+jHQ9QncbIFOUdsZF12jafClYB9X/JIjfzACzHSsPqg60ROmwB8Nzd+9RdY2i+EOScI7laJsiCiuacZ7mUCy32NUTU2aGGLkt6TUia2BRQuiHJg+smkl6WfVdCRzf2JvXHvxcUKpNjXO52lJW9t/9Noe36ai/PgoylBTR6QU+MADPFFILaNO6Z9ST9O/3mnvgNA55pydnP53Q== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB9PR04MB9236.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(6666004)(186003)(1076003)(38100700002)(52116002)(38350700002)(2616005)(26005)(86362001)(6512007)(36756003)(66476007)(4326008)(5660300002)(83380400001)(66556008)(8936002)(66946007)(8676002)(2906002)(6506007)(316002)(508600001)(6486002);DIR:OUT;SFP:1101; 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Obviously, the Linux itself optimizes the MPS settings in the PCIE_BUS_SAFE and PCIE_BUS_PERFORMANCE mode, so let's do this also for these modes. Signed-off-by: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- drivers/pci/probe.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 17a969942d37..2c5a1aefd9cb 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2034,7 +2034,9 @@ static void pci_configure_mps(struct pci_dev *dev) * Fancier MPS configuration is done later by * pcie_bus_configure_settings() */ - if (pcie_bus_config != PCIE_BUS_DEFAULT) + if (pcie_bus_config != PCIE_BUS_DEFAULT && + pcie_bus_config != PCIE_BUS_SAFE && + pcie_bus_config != PCIE_BUS_PERFORMANCE) return; mpss = 128 << dev->pcie_mpss; @@ -2047,7 +2049,7 @@ static void pci_configure_mps(struct pci_dev *dev) rc = pcie_set_mps(dev, p_mps); if (rc) { - pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", + pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_peer2peer\" and report a bug\n", p_mps); return; }