| Message ID | 20220629141000.18111-5-johan+linaro@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: qcom: Add support for SC8280XP and SA8540P | expand |
On 29/06/2022 16:09, Johan Hovold wrote: > Add the SC8280XP platform to the binding. > > SC8280XP use four host interrupts for MSI routing so remove the obsolete > comment referring to newer chipsets supporting one or eight interrupts > (e.g. for backwards compatibility). > (...) > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sc8280xp > + then: > + properties: > + interrupts: > + minItems: 4 > + maxItems: 4 > + interrupt-names: > + items: > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 What the previous #3 commit is missing is: "This allows for adding further platforms with for example four MSI interrupts, without resorting to nested conditionals." Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Jul 01, 2022 at 10:37:55AM +0200, Krzysztof Kozlowski wrote: > On 29/06/2022 16:09, Johan Hovold wrote: > > Add the SC8280XP platform to the binding. > > > > SC8280XP use four host interrupts for MSI routing so remove the obsolete > > comment referring to newer chipsets supporting one or eight interrupts > > (e.g. for backwards compatibility). > > > > (...) > > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - qcom,pcie-sc8280xp > > + then: > > + properties: > > + interrupts: > > + minItems: 4 > > + maxItems: 4 > > + interrupt-names: > > + items: > > + - const: msi0 > > + - const: msi1 > > + - const: msi2 > > + - const: msi3 > > What the previous #3 commit is missing is: > "This allows for adding further platforms with for example four MSI > interrupts, without resorting to nested conditionals." Yeah, that would make the comment more self-contained. I'll amend it if I need to respin. Johan
On Wed, Jun 29, 2022 at 04:09:54PM +0200, Johan Hovold wrote: > Add the SC8280XP platform to the binding. > > SC8280XP use four host interrupts for MSI routing so remove the obsolete > comment referring to newer chipsets supporting one or eight interrupts > (e.g. for backwards compatibility). > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Wondering why 4 on this SoC. Is this what added in downstream or you also verified it with IP documentation. Thanks, Mani > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++- > 1 file changed, 49 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 8560c65e6f0b..a039f6110322 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -27,6 +27,7 @@ properties: > - qcom,pcie-qcs404 > - qcom,pcie-sc7280 > - qcom,pcie-sc8180x > + - qcom,pcie-sc8280xp > - qcom,pcie-sdm845 > - qcom,pcie-sm8150 > - qcom,pcie-sm8250 > @@ -181,6 +182,7 @@ allOf: > enum: > - qcom,pcie-sc7280 > - qcom,pcie-sc8180x > + - qcom,pcie-sc8280xp > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > @@ -596,6 +598,35 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sc8280xp > + then: > + properties: > + clocks: > + minItems: 8 > + maxItems: 9 > + clock-names: > + minItems: 8 > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: noc_aggr_4 # NoC aggregate 4 clock > + - const: noc_aggr_south_sf # NoC aggregate South SF clock > + - const: cnoc_qx # Configuration NoC QX clock > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: pci # PCIe core reset > + > - if: > not: > properties: > @@ -624,7 +655,6 @@ allOf: > - resets > - reset-names > > - # On newer chipsets support either 1 or 8 msi interrupts > - if: > properties: > compatible: > @@ -660,6 +690,24 @@ allOf: > - const: msi6 > - const: msi7 > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sc8280xp > + then: > + properties: > + interrupts: > + minItems: 4 > + maxItems: 4 > + interrupt-names: > + items: > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 > + > - if: > properties: > compatible: > -- > 2.35.1 >
On Sat, Jul 09, 2022 at 01:30:53PM +0530, Manivannan Sadhasivam wrote: > On Wed, Jun 29, 2022 at 04:09:54PM +0200, Johan Hovold wrote: > > Add the SC8280XP platform to the binding. > > > > SC8280XP use four host interrupts for MSI routing so remove the obsolete > > comment referring to newer chipsets supporting one or eight interrupts > > (e.g. for backwards compatibility). > > > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > > Wondering why 4 on this SoC. Is this what added in downstream or you also > verified it with IP documentation. I don't have direct access to the IP docs, but I've verified it with people who do. Johan
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 8560c65e6f0b..a039f6110322 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -27,6 +27,7 @@ properties: - qcom,pcie-qcs404 - qcom,pcie-sc7280 - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 @@ -181,6 +182,7 @@ allOf: enum: - qcom,pcie-sc7280 - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 @@ -596,6 +598,35 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + clocks: + minItems: 8 + maxItems: 9 + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: not: properties: @@ -624,7 +655,6 @@ allOf: - resets - reset-names - # On newer chipsets support either 1 or 8 msi interrupts - if: properties: compatible: @@ -660,6 +690,24 @@ allOf: - const: msi6 - const: msi7 + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - if: properties: compatible:
Add the SC8280XP platform to the binding. SC8280XP use four host interrupts for MSI routing so remove the obsolete comment referring to newer chipsets supporting one or eight interrupts (e.g. for backwards compatibility). Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-)