From patchwork Fri Jul 15 03:04:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12918691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F04EC43334 for ; Fri, 15 Jul 2022 03:05:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241303AbiGODFf (ORCPT ); Thu, 14 Jul 2022 23:05:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241263AbiGODFE (ORCPT ); Thu, 14 Jul 2022 23:05:04 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5854E67160; Thu, 14 Jul 2022 20:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657854303; x=1689390303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=du+1VWLCHVjOapuMlx5AwDnUCvU9qYGbjlO6VboghMU=; b=GVxNRMssQVGcTsfN00rsXkI10cfO8+dV05LbnWQ+SGPLpkLL9nbRDjf5 Xe43jJ3LQ84EbZidBLWRamLX99rrXOyWGzTUUyZKs4/rDSPiWEwV/Iibg ilSnZPILdtVXk/L7Tft4tvn52WCnweT2Nugmf+KLwTYW0yE3lGhJik7Sa RCSP5pO6cxMlSyap6PhFa+KC6xVLGPnFRtCgEOn3tgdyjiGr+SUsAu8Ml Y2mEkenUBR/RM/E3rPHUWdExViKmJqTdKYPxiprP9lu/FFFyjg9PP+1/y wMOayu3c2GmbEx3rmDJkLRls0UDV/seUe48KJCjgQp05ZlassfdLR+ktw Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="266100505" X-IronPort-AV: E=Sophos;i="5.92,272,1650956400"; d="scan'208";a="266100505" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 20:05:03 -0700 X-IronPort-AV: E=Sophos;i="5.92,272,1650956400"; d="scan'208";a="664028207" Received: from mbordone-mobl.amr.corp.intel.com (HELO localhost) ([10.255.5.217]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 20:05:00 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Ira Weiny , Lukas Wunner , Alison Schofield , Vishal Verma , Dave Jiang , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid() Date: Thu, 14 Jul 2022 20:04:24 -0700 Message-Id: <20220715030424.462963-8-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220715030424.462963-1-ira.weiny@intel.com> References: <20220715030424.462963-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ira Weiny The CDAT data is protected by a checksum and should be the proper length. Introduce cxl_cdat_valid() to validate the data. While at it check and store the sequence number. Signed-off-by: Ira Weiny --- Changes from V12 Jonathan: Remove unneeded rc check. Changes from V8 Move code to cxl/core/pci.c Changes from V6 Change name to cxl_cdat_valid() as this validates all the CDAT data not just the header Add error and debug prints Changes from V5 New patch, split out Update cdat_hdr_valid() Remove revision and cs field parsing There is no point in these Add seq check and debug print. --- drivers/cxl/cdat.h | 2 ++ drivers/cxl/core/pci.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h index 67010717ffca..162ef474ee5a 100644 --- a/drivers/cxl/cdat.h +++ b/drivers/cxl/cdat.h @@ -52,10 +52,12 @@ * * @table: cache of CDAT table * @length: length of cached CDAT table + * @seq: Last read Sequence number of the CDAT table */ struct cxl_cdat { void *table; size_t length; + u32 seq; }; #endif /* !__CXL_CDAT_H__ */ diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index dd5d1da412ca..36e14549997d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -529,6 +529,40 @@ static int cxl_cdat_get_length(struct device *dev, return 0; } +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat) +{ + u32 *table = cdat->table; + u8 *data8 = cdat->table; + u32 length, seq; + u8 check; + int i; + + length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]); + if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) { + dev_err(dev, "CDAT Invalid length %u (%zu-%zu)\n", length, + CDAT_HEADER_LENGTH_BYTES, cdat->length); + return false; + } + + for (check = 0, i = 0; i < length; i++) + check += data8[i]; + + dev_dbg(dev, "CDAT length %u CS %u\n", length, check); + if (check != 0) { + dev_err(dev, "CDAT Invalid checksum %u\n", check); + return false; + } + + seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]); + /* Store the sequence for now. */ + if (cdat->seq != seq) { + dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq); + cdat->seq = seq; + } + + return true; +} + static int cxl_cdat_read_table(struct device *dev, struct pci_doe_mb *cdat_doe, struct cxl_cdat *cdat) @@ -576,6 +610,9 @@ static int cxl_cdat_read_table(struct device *dev, } } while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY); + if (!cxl_cdat_valid(dev, cdat)) + return -EIO; + return 0; }