Message ID | 20220721142052.25971-12-vidyas@nvidia.com (mailing list archive) |
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State | Accepted |
Headers | show
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Thu, 21 Jul 2022 14:22:24 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 21 Jul 2022 07:22:23 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 21 Jul 2022 07:22:19 -0700 From: Vidya Sagar <vidyas@nvidia.com> To: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com> CC: <kw@linux.com>, <kishon@ti.com>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com> Subject: [PATCH V6 11/16] PCI: tegra194: Clear bandwidth management status Date: Thu, 21 Jul 2022 19:50:47 +0530 Message-ID: <20220721142052.25971-12-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220721142052.25971-1-vidyas@nvidia.com> References: <20220721142052.25971-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d5084094-1cfa-46ef-229c-08da6b246ed9 X-MS-TrafficTypeDiagnostic: SJ0PR12MB5485:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
PCI: tegra: Add Tegra234 PCIe support
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expand
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diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 23377425952a..5f1798d37572 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -370,6 +370,12 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) apply_bad_link_workaround(pp); } if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + + PCI_EXP_LNKSTA); + val_w |= PCI_EXP_LNKSTA_LBMS; + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + + PCI_EXP_LNKSTA, val_w); + appl_writel(pcie, APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS, APPL_INTR_STATUS_L1_8_0);
In the event of a bandwidth management interrupt, clear the bandwidth management status in the configuration space also along with clearing corresponding status in the application logic register to avoid slew of interrupts. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V6: * New addition in V6 based on Bjorn's review comment drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++++++ 1 file changed, 6 insertions(+)