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Thu, 21 Jul 2022 14:22:49 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 21 Jul 2022 07:22:49 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 21 Jul 2022 07:22:45 -0700 From: Vidya Sagar To: , , , , , , , CC: , , , , , , , , , Subject: [PATCH V6 15/16] PCI: tegra194: Extend endpoint mode support Date: Thu, 21 Jul 2022 19:50:51 +0530 Message-ID: <20220721142052.25971-16-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220721142052.25971-1-vidyas@nvidia.com> References: <20220721142052.25971-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1409ad5d-848e-4803-f994-08da6b247e1c X-MS-TrafficTypeDiagnostic: SA0PR12MB4526:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2022 14:22:50.3919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1409ad5d-848e-4803-f994-08da6b247e1c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4526 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since only Controller-5 can be used in the endpoint mode in P2972-0000 platform, support is available only for Controller-5. This patch extends that support by enabling the endpoint mode capable controller during initialization phase which otherwise is not required if it is only Controller-5. Signed-off-by: Vidya Sagar --- V6: * New addition in V6 based on Bjorn's review comment drivers/pci/controller/dwc/pcie-tegra194.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index bac2e1ad0a29..fc373b6efd00 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1650,6 +1650,13 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) return; } + ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true); + if (ret) { + dev_err(pcie->dev, "Failed to enable controller %u: %d\n", + pcie->cid, ret); + goto fail_set_ctrl_state; + } + ret = tegra_pcie_bpmp_set_pll_state(pcie, true); if (ret) { dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret); @@ -1798,6 +1805,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) fail_core_clk_enable: tegra_pcie_bpmp_set_pll_state(pcie, false); fail_pll_init: + tegra_pcie_bpmp_set_ctrl_state(pcie, false); +fail_set_ctrl_state: pm_runtime_put_sync(dev); }