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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2022 14:21:26.4334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c67f7712-7f38-425f-758a-08da6b244c1b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5400 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for PCIe controllers that operate in the rootport mode in tegra234 chipset. Signed-off-by: Vidya Sagar Reviewed-by: Rob Herring --- V6: * Added 'Reviewed-by: Rob Herring ' V5: * Addressed review comments from Rob V4: * Rebased on top of previous patch V3: * New patch in this series .../bindings/pci/nvidia,tegra194-pcie.yaml | 102 +++++++++++++++++- 1 file changed, 100 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml index abbaafe98fd4..1e2274b2ba0b 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml @@ -24,6 +24,7 @@ properties: compatible: enum: - nvidia,tegra194-pcie + - nvidia,tegra234-pcie reg: items: @@ -92,7 +93,8 @@ properties: A phandle to the node that controls power to the respective PCIe controller and a specifier name for the PCIe controller. - specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file. + Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file. + Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" file. interconnects: items: @@ -112,17 +114,34 @@ properties: Must contain a pair of phandle to BPMP controller node followed by controller ID. Following are the controller IDs for each controller: + Tegra194 + 0: C0 1: C1 2: C2 3: C3 4: C4 5: C5 + + Tegra234 + + 0 : C0 + 1 : C1 + 2 : C2 + 3 : C3 + 4 : C4 + 5 : C5 + 6 : C6 + 7 : C7 + 8 : C8 + 9 : C9 + 10: C10 + items: - items: - description: phandle to BPMP controller node - description: PCIe controller ID - maximum: 5 + maximum: 10 nvidia,update-fc-fixup: description: | @@ -131,6 +150,8 @@ properties: of the following conditions thereby enabling root port to exchange optimum number of FC (Flow Control) credits with downstream devices: + NOTE:- This is applicable only for Tegra194. + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and a) speed is Gen-2 and MPS is 256B @@ -162,6 +183,22 @@ properties: if the platform has one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform). + nvidia,enable-srns: + description: | + This boolean property needs to be present if the controller is configured + to operate in SRNS (Separate Reference Clocks with No Spread-Spectrum Clocking). + NOTE:- This is applicable only for Tegra234. + + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,enable-ext-refclk: + description: | + This boolean property needs to be present if the controller is configured + to use the reference clocking coming in from an external clock source instead of + using the internal clock source. + + $ref: /schemas/types.yaml#/definitions/flag + allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# @@ -249,3 +286,64 @@ examples: phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; }; }; + + - | + #include + #include + #include + #include + + bus@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x8 0x0>; + + pcie@14160000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <4>; + + clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; + + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + nvidia,bpmp = <&bpmp 4>; + + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */ + <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */ + <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */ + + vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + };