@@ -1659,12 +1659,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
goto fail_pm_get_sync;
}
- ret = pinctrl_pm_select_default_state(dev);
- if (ret < 0) {
- dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
- goto fail_pm_get_sync;
- }
-
ret = tegra_pcie_init_controller(pcie);
if (ret < 0) {
dev_err(dev, "Failed to initialize controller: %d\n", ret);
@@ -2120,6 +2114,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pp = &pci->pp;
pp->num_vectors = MAX_MSI_IRQS;
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret < 0) {
+ const char *level = KERN_ERR;
+
+ if (ret == -EPROBE_DEFER)
+ level = KERN_DEBUG;
+
+ dev_printk(level, dev,
+ "Failed to configure sideband pins: %d\n",
+ ret);
+ return ret;
+ }
+
ret = tegra_pcie_dw_parse_dt(pcie);
if (ret < 0) {
const char *level = KERN_ERR;
PERST# and CLKREQ# pinctrl settings should be applied for both root port and endpoint mode. Move pinctrl_pm_select_default_state() function call from root port specific configuration function to probe(). Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-)