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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:17.5418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af831bb4-a975-43eb-c292-08daad4a600c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5911 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Call dw_pcie_ep_deinit() during controller deinitialization to free the resources allocated in common DesignWare driver. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 910dc6c2154e..7820bf4b9786 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1770,12 +1770,16 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) { + struct dw_pcie *pci = &pcie->pci; + struct dw_pcie_ep *ep = &pci->ep; u32 val; int ret; if (pcie->ep_state == EP_STATE_DISABLED) return; + dw_pcie_ep_deinit_notify(ep); + ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||