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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:43.3267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccc82c90-7468-4685-9097-08daad4a4ba5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6549 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PERST# and CLKREQ# pinctrl settings should be applied for both root port and endpoint mode. Move pinctrl_pm_select_default_state() function call from root port specific configuration function to probe(). Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index ae7e0d8f693b..69e11a74a0d7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1716,12 +1716,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - ret = pinctrl_pm_select_default_state(dev); - if (ret < 0) { - dev_err(dev, "Failed to configure sideband pins: %d\n", ret); - goto fail_pm_get_sync; - } - ret = tegra_pcie_init_controller(pcie); if (ret < 0) { dev_err(dev, "Failed to initialize controller: %d\n", ret); @@ -2191,6 +2185,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; + ret = pinctrl_pm_select_default_state(dev); + if (ret < 0) { + const char *level = KERN_ERR; + + if (ret == -EPROBE_DEFER) + level = KERN_DEBUG; + + dev_printk(level, dev, + "Failed to configure sideband pins: %d\n", + ret); + return ret; + } + ret = tegra_pcie_dw_parse_dt(pcie); if (ret < 0) { const char *level = KERN_ERR;