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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 08:36:11.9752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0ef1cd8-1fe1-414f-b5e2-08dacdf6f15b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5937 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra234 supports PCIe lane margining. P2U HW acts as a relay to exchange margin control data and margin status between PCIe controller and UPHY. Signed-off-by: Manikanta Maddireddy --- .../bindings/phy/phy-tegra194-p2u.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml index 4dc5205d893b..0ba3f6a0b474 100644 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml @@ -40,6 +40,51 @@ properties: '#phy-cells': const: 0 + interrupts: + items: + description: P2U interrupt for Gen4 lane margining functionality. + + interrupt-names: + items: + - const: intr + + nvidia,bpmp: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Must contain a pair of phandles to BPMP controller node followed by P2U ID. + items: + - items: + - description: phandle to BPMP controller node + - description: P2U instance ID + maximum: 24 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-p2u + then: + required: + - reg + - reg-names + - '#phy-cells' + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-p2u + then: + required: + - reg + - reg-names + - '#phy-cells' + - interrupts + - interrupt-names + - nvidia,bpmp + additionalProperties: false examples: @@ -49,5 +94,10 @@ examples: reg = <0x03e10000 0x10000>; reg-names = "ctl"; + interrupts = <0 337 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 1>; + #phy-cells = <0>; };