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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 08:36:17.6050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39f04390-7b88-4dc3-c13e-08dacdf6f4b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5087 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org UPHY lane number is required to exchange lane margin data between P2U and UPHY. Add uphy lane number in p2u device tree nodes. Signed-off-by: Manikanta Maddireddy --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 120 +++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index eaf05ee9acd1..ec8a28a9d380 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1109,6 +1109,11 @@ p2u_hsio_0: phy@3e00000 { reg = <0x03e00000 0x10000>; reg-names = "ctl"; + interrupts = <0 336 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 0>; + #phy-cells = <0>; }; @@ -1117,6 +1122,11 @@ p2u_hsio_1: phy@3e10000 { reg = <0x03e10000 0x10000>; reg-names = "ctl"; + interrupts = <0 337 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 1>; + #phy-cells = <0>; }; @@ -1125,6 +1135,11 @@ p2u_hsio_2: phy@3e20000 { reg = <0x03e20000 0x10000>; reg-names = "ctl"; + interrupts = <0 338 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 2>; + #phy-cells = <0>; }; @@ -1133,6 +1148,11 @@ p2u_hsio_3: phy@3e30000 { reg = <0x03e30000 0x10000>; reg-names = "ctl"; + interrupts = <0 339 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 3>; + #phy-cells = <0>; }; @@ -1141,6 +1161,11 @@ p2u_hsio_4: phy@3e40000 { reg = <0x03e40000 0x10000>; reg-names = "ctl"; + interrupts = <0 340 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 4>; + #phy-cells = <0>; }; @@ -1149,6 +1174,11 @@ p2u_hsio_5: phy@3e50000 { reg = <0x03e50000 0x10000>; reg-names = "ctl"; + interrupts = <0 341 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 5>; + #phy-cells = <0>; }; @@ -1157,6 +1187,11 @@ p2u_hsio_6: phy@3e60000 { reg = <0x03e60000 0x10000>; reg-names = "ctl"; + interrupts = <0 342 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 6>; + #phy-cells = <0>; }; @@ -1165,6 +1200,11 @@ p2u_hsio_7: phy@3e70000 { reg = <0x03e70000 0x10000>; reg-names = "ctl"; + interrupts = <0 343 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 7>; + #phy-cells = <0>; }; @@ -1173,6 +1213,11 @@ p2u_nvhs_0: phy@3e90000 { reg = <0x03e90000 0x10000>; reg-names = "ctl"; + interrupts = <0 344 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 8>; + #phy-cells = <0>; }; @@ -1181,6 +1226,11 @@ p2u_nvhs_1: phy@3ea0000 { reg = <0x03ea0000 0x10000>; reg-names = "ctl"; + interrupts = <0 345 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 9>; + #phy-cells = <0>; }; @@ -1189,6 +1239,11 @@ p2u_nvhs_2: phy@3eb0000 { reg = <0x03eb0000 0x10000>; reg-names = "ctl"; + interrupts = <0 346 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 10>; + #phy-cells = <0>; }; @@ -1197,6 +1252,11 @@ p2u_nvhs_3: phy@3ec0000 { reg = <0x03ec0000 0x10000>; reg-names = "ctl"; + interrupts = <0 347 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 11>; + #phy-cells = <0>; }; @@ -1205,6 +1265,11 @@ p2u_nvhs_4: phy@3ed0000 { reg = <0x03ed0000 0x10000>; reg-names = "ctl"; + interrupts = <0 348 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 12>; + #phy-cells = <0>; }; @@ -1213,6 +1278,11 @@ p2u_nvhs_5: phy@3ee0000 { reg = <0x03ee0000 0x10000>; reg-names = "ctl"; + interrupts = <0 349 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 13>; + #phy-cells = <0>; }; @@ -1221,6 +1291,11 @@ p2u_nvhs_6: phy@3ef0000 { reg = <0x03ef0000 0x10000>; reg-names = "ctl"; + interrupts = <0 350 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 14>; + #phy-cells = <0>; }; @@ -1229,6 +1304,11 @@ p2u_nvhs_7: phy@3f00000 { reg = <0x03f00000 0x10000>; reg-names = "ctl"; + interrupts = <0 351 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 15>; + #phy-cells = <0>; }; @@ -1237,6 +1317,11 @@ p2u_gbe_0: phy@3f20000 { reg = <0x03f20000 0x10000>; reg-names = "ctl"; + interrupts = <0 203 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 16>; + #phy-cells = <0>; }; @@ -1245,6 +1330,11 @@ p2u_gbe_1: phy@3f30000 { reg = <0x03f30000 0x10000>; reg-names = "ctl"; + interrupts = <0 220 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 17>; + #phy-cells = <0>; }; @@ -1253,6 +1343,11 @@ p2u_gbe_2: phy@3f40000 { reg = <0x03f40000 0x10000>; reg-names = "ctl"; + interrupts = <0 221 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 18>; + #phy-cells = <0>; }; @@ -1261,6 +1356,11 @@ p2u_gbe_3: phy@3f50000 { reg = <0x03f50000 0x10000>; reg-names = "ctl"; + interrupts = <0 222 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 19>; + #phy-cells = <0>; }; @@ -1269,6 +1369,11 @@ p2u_gbe_4: phy@3f60000 { reg = <0x03f60000 0x10000>; reg-names = "ctl"; + interrupts = <0 108 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 20>; + #phy-cells = <0>; }; @@ -1277,6 +1382,11 @@ p2u_gbe_5: phy@3f70000 { reg = <0x03f70000 0x10000>; reg-names = "ctl"; + interrupts = <0 109 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 21>; + #phy-cells = <0>; }; @@ -1285,6 +1395,11 @@ p2u_gbe_6: phy@3f80000 { reg = <0x03f80000 0x10000>; reg-names = "ctl"; + interrupts = <0 110 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 22>; + #phy-cells = <0>; }; @@ -1293,6 +1408,11 @@ p2u_gbe_7: phy@3f90000 { reg = <0x03f90000 0x10000>; reg-names = "ctl"; + interrupts = <0 111 0x04>; + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 23>; + #phy-cells = <0>; };