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Thu, 24 Nov 2022 13:58:56 +0000 From: Vadym Kochan To: Thomas Petazzoni , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Elad Nachman , Vadym Kochan , Yuval Shaia Subject: [PATCH v2 3/3] PCI: armada8k: Add MSI support for AC5 SoC Date: Thu, 24 Nov 2022 15:58:28 +0200 Message-Id: <20221124135829.2551873-4-vadym.kochan@plvision.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124135829.2551873-1-vadym.kochan@plvision.eu> References: <20221124135829.2551873-1-vadym.kochan@plvision.eu> X-ClientProxiedBy: FR3P281CA0120.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a3::18) To VI1P190MB0317.EURP190.PROD.OUTLOOK.COM (2603:10a6:802:38::26) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1P190MB0317:EE_|AM7P190MB0758:EE_ X-MS-Office365-Filtering-Correlation-Id: 779bcf49-8303-42fe-c21b-08dace24070d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Fix it by: 1. Enabling the relevant bits in init phase 2. Dispatch virtual IRQ handlers when MSI interrupts are received Also enable/disable PCIE_APP_LTSSM for AC5. Signed-off-by: Yuval Shaia Signed-off-by: Vadym Kochan --- v2: 1) fix W1 warnings which caused by unused leftover code 2) fix type in "requieres" word in the description drivers/pci/controller/dwc/pcie-armada8k.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index bbe9a1750d0d..7e02eddaeac0 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -50,6 +50,7 @@ struct armada8k_pcie_of_data { #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) +#define PCIE_APP_LTSSM_EN_AC5 BIT(24) #define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ @@ -69,6 +70,7 @@ struct armada8k_pcie_of_data { #define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13) #define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14) #define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15) +#define PCIE_MSI_MASK_AC5 BIT(11) #define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20) @@ -172,6 +174,16 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) return 0; } +static void ac5_pcie_msi_init(struct dw_pcie *pci) +{ + u32 val; + + /* Set MSI bit in interrupt mask */ + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); + val |= PCIE_MSI_MASK_AC5; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val); +} + static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { u32 reg; @@ -181,7 +193,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &= ~(PCIE_APP_LTSSM_EN); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) + reg &= ~(PCIE_APP_LTSSM_EN_AC5); + else + reg &= ~(PCIE_APP_LTSSM_EN); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } @@ -221,6 +236,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); } + if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + ac5_pcie_msi_init(pci); + return 0; } @@ -237,6 +255,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) + dw_handle_msi_irq(&pci->pp); return IRQ_HANDLED; }