Message ID | 20230118125936.3456716-6-a-verma1@ti.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Lorenzo Pieralisi |
Headers | show |
Series | PCI: add 4x lane support for pci-j721e controllers | expand |
If you repost for some other reason, fix the subject typo ("Add ..." to match the others). Otherwise, Lorenzo may fix it up while applying. On Wed, Jan 18, 2023 at 06:29:36PM +0530, Achal Verma wrote: > From: Matt Ranostay <mranostay@ti.com> > > Add PCIe configuration for j784s4 platform which has 4x lane support. > > Tested-by: Achal Verma <a-verma1@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Reviewed-by: Roger Quadros <rogerq@kernel.org> > Signed-off-by: Achal Verma <a-verma1@ti.com>
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 58dcac9021e4..cce7b391f931 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, };