| Message ID | 20230223180531.15148-8-enachman@marvell.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: dwc: Add support for Marvell AC5 SoC | expand |
On 23/02/2023 19:05, Elad Nachman wrote: > From: Elad Nachman <enachman@marvell.com> > > Allow dts override of region limit for SOCs with older Synopsis > Designware PCIe IP but with greater than 32-bit address range support, > such as the Armada 7020/7040/8040 family of SOCs by Marvell, > when the DT file places the PCIe window above the 4GB region. > The Synopsis Designware PCIe IP in these SOCs is too old to specify the > highest memory location supported by the PCIe, but practically supports > such locations. Allow these locations to be specified in the DT file. > DT property is called num-regionmask , and can range between 33 and 64. > > Signed-off-by: Elad Nachman <enachman@marvell.com> > --- > drivers/pci/controller/dwc/pcie-designware.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 53a16b8b6ac2..429594e853ae 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -401,7 +401,6 @@ static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, > int ret; > > base = dw_pcie_select_atu(pci, dir, index); > - > if (pci->ops && pci->ops->write_dbi) { > pci->ops->write_dbi(pci, base, reg, 4, val); > return; > @@ -735,10 +734,13 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) > void dw_pcie_iatu_detect(struct dw_pcie *pci) > { > int max_region, ob, ib; > - u32 val, min, dir; > + u32 val, min, dir, ret, num_region_maskbits; No need to use num_region_maskbits in function scope. > u64 max; > + struct device *dev = pci->dev; > + struct device_node *np = dev->of_node; > > val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); > + You need to fix this random changes in unrelated places... Best regards, Krzysztof
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 53a16b8b6ac2..429594e853ae 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -401,7 +401,6 @@ static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, int ret; base = dw_pcie_select_atu(pci, dir, index); - if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, base, reg, 4, val); return; @@ -735,10 +734,13 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) void dw_pcie_iatu_detect(struct dw_pcie *pci) { int max_region, ob, ib; - u32 val, min, dir; + u32 val, min, dir, ret, num_region_maskbits; u64 max; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + if (val == 0xFFFFFFFF) { dw_pcie_cap_set(pci, IATU_UNROLL); @@ -781,7 +783,12 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); } else { - max = 0; + /* Allow dts override of region limit for older IP with above 32-bit support: */ + ret = of_property_read_u32(np, "num-regionmask", &num_region_maskbits); + if (!ret && num_region_maskbits > 32) + max = GENMASK(num_region_maskbits - 33, 0); + else + max = 0; } pci->num_ob_windows = ob;