Message ID | 20230308082424.140224-3-manivannan.sadhasivam@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Krzysztof WilczyĆski |
Headers | show |
Series | Add PCIe RC support to Qcom SDX55 SoC | expand |
On Wed, 08 Mar 2023 13:54:13 +0530, Manivannan Sadhasivam wrote: > Most of the PCIe controllers require iommu support to function properly. > So let's add the "iommu-map" property that specifies the SMMU SID of the > PCIe devices to the binding. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 92eb273581f6..55ee86facbc0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -70,6 +70,8 @@ properties: dma-coherent: true + iommu-map: true + interconnects: maxItems: 2
Most of the PCIe controllers require iommu support to function properly. So let's add the "iommu-map" property that specifies the SMMU SID of the PCIe devices to the binding. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ 1 file changed, 2 insertions(+)