From patchwork Fri Mar 10 04:08:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13168699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A57AC6FA99 for ; Fri, 10 Mar 2023 04:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231151AbjCJEMY (ORCPT ); Thu, 9 Mar 2023 23:12:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230459AbjCJEK5 (ORCPT ); Thu, 9 Mar 2023 23:10:57 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75920102B78 for ; Thu, 9 Mar 2023 20:09:44 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id s17so2358190pgv.4 for ; Thu, 09 Mar 2023 20:09:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=hYP3bxNUWN+cDM56wIW5jHqBMTGJY5MpDds/b+AcTuqU6Tl+GBM8Hdk/iy+xZLDU2Q LcFhkkJUAtLBLgGDQ/FBdnvsSeBT6rNX/xwSUH1Rw3FpovXy0cg2cJnZ62a4hOB7CUYr i/I6hUAVAvdnO3eTnp0gu2SIlf4teIBioRdcUFmuFXjrIRdsDwRgYCKetGSr2/5aV/5z 1wVtpdwJ/4DwFiDh2SM4QxN6b+zAb+uGIkW6e7mIZnZJj+dMwzJaLw2no2q+DGqEzwi1 77nXkAWzhmrDqYE27e+rkYYSXkqql9u66ySYgu9LSWUcxl85iKlXBqoMtHTTGum4a+7V e9iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=1jvZ//rnGqh8y3ANYjIn5GqeSJMZ16FeMTy552EF6mGAz9Aea0DiZzbozuMYzwk72f WTk2rGnFwubD8Z5R0NiNpsXKNvNxauYHV8jiSnrKEj4KoLxy7K9YICgIhp+ysFWY4r5Z oqQG4EB3KcDN4LPJAgIw3e9bNJqf9HEC+ess2anhaDGi1KyWQcPUNjHNeFGbxSqpkZo8 IZdhhwTttvW36uf0gQjiiNo69mK4x8FLW7wwtB3KzXc8E1QO1tkgbw9brrM3dxHg97Pg W+wax0KNp5LMWWcsFVMPkHM1k6Dg91mZLoY3kqbFF0VXi4950/x++kFDEXFbOO6fM7mk rOtg== X-Gm-Message-State: AO0yUKVq2jAArY4254hKQlAmQJIGmANC/7SBT0JXB/PPT/GJ4UTP/tB9 xStRjuHoZfXfJTpfsMrusvem X-Google-Smtp-Source: AK7set/4pNSj969315rt8pVl6hBMGuJfDedYhhW2cJ8CkAfOk42sbXlP+vWpBfjIMWj/N3WmPsGiwg== X-Received: by 2002:aa7:968e:0:b0:5a9:bba9:f25b with SMTP id f14-20020aa7968e000000b005a9bba9f25bmr23736644pfk.17.1678421384135; Thu, 09 Mar 2023 20:09:44 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:42 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 17/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes Date: Fri, 10 Mar 2023 09:38:14 +0530 Message-Id: <20230310040816.22094-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..eb87c3e5d2bc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1653,8 +1653,9 @@ pcie4: pcie@1c00000 { <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, - <0x0 0x30100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x30100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, @@ -1752,8 +1753,9 @@ pcie3b: pcie@1c08000 { <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, - <0x0 0x32100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x32100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, @@ -1849,8 +1851,9 @@ pcie3a: pcie@1c10000 { <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, - <0x0 0x34100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x34100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, @@ -1949,8 +1952,9 @@ pcie2b: pcie@1c18000 { <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, - <0x0 0x38100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x38100000 0x0 0x100000>, + <0x0 0x01c1b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, @@ -2046,8 +2050,9 @@ pcie2a: pcie@1c20000 { <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, - <0x0 0x3c100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,