| Message ID | 20230310040816.22094-20-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Qcom PCIe cleanups and improvements | expand |
On 3/10/2023 9:38 AM, Manivannan Sadhasivam wrote: > Qualcomm PCIe controllers of version v2.4.0 have debug registers in the > PARF region that count PCIe link transitions. Expose them over debugfs to > userspace to help debug the low power issues. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 33 ++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index f99b7e7f3f73..0b41f007fa90 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -37,6 +37,7 @@ > /* PARF registers */ > #define PARF_SYS_CTRL 0x00 > #define PARF_PM_CTRL 0x20 > +#define PARF_PM_STTS 0x24 > #define PARF_PCS_DEEMPH 0x34 > #define PARF_PCS_SWING 0x38 > #define PARF_PHY_CTRL 0x40 > @@ -84,6 +85,12 @@ > /* PARF_PM_CTRL register fields */ > #define REQ_NOT_ENTR_L1 BIT(5) > > +/* PARF_PM_STTS register fields */ > +#define PM_LINKST_IN_L1SUB BIT(8) > +#define PM_LINKST_IN_L0S BIT(7) > +#define PM_LINKST_IN_L2 BIT(5) > +#define PM_LINKST_IN_L1 BIT(4) > + > /* PARF_PCS_DEEMPH register fields */ > #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) > #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) > @@ -737,6 +744,31 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) > return 0; > } > > +static int qcom_pcie_debugfs_func_2_4_0(struct seq_file *s, void *data) > +{ > + struct qcom_pcie *pcie = (struct qcom_pcie *) dev_get_drvdata(s->private); > + > + seq_printf(s, "L0s transition count: %u\n", > + readl_relaxed(pcie->parf + PM_LINKST_IN_L0S)); > + > + seq_printf(s, "L1 transition count: %u\n", > + readl_relaxed(pcie->parf + PM_LINKST_IN_L1)); > + > + seq_printf(s, "L1.1 transition count: %u\n", > + readl_relaxed(pcie->parf + PM_LINKST_IN_L1SUB)); > + > + seq_printf(s, "L2 transition count: %u\n", > + readl_relaxed(pcie->parf + PM_LINKST_IN_L2)); > + Using bitmask as register offset ? instead use PM_STTS and bitmask it ? Regards, Sricharan
On 3/14/2023 4:06 PM, Sricharan Ramabadhran wrote: > > > On 3/10/2023 9:38 AM, Manivannan Sadhasivam wrote: >> Qualcomm PCIe controllers of version v2.4.0 have debug registers in the >> PARF region that count PCIe link transitions. Expose them over debugfs to >> userspace to help debug the low power issues. >> >> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 33 ++++++++++++++++++++++++++ >> 1 file changed, 33 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >> b/drivers/pci/controller/dwc/pcie-qcom.c >> index f99b7e7f3f73..0b41f007fa90 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -37,6 +37,7 @@ >> /* PARF registers */ >> #define PARF_SYS_CTRL 0x00 >> #define PARF_PM_CTRL 0x20 >> +#define PARF_PM_STTS 0x24 >> #define PARF_PCS_DEEMPH 0x34 >> #define PARF_PCS_SWING 0x38 >> #define PARF_PHY_CTRL 0x40 >> @@ -84,6 +85,12 @@ >> /* PARF_PM_CTRL register fields */ >> #define REQ_NOT_ENTR_L1 BIT(5) >> +/* PARF_PM_STTS register fields */ >> +#define PM_LINKST_IN_L1SUB BIT(8) >> +#define PM_LINKST_IN_L0S BIT(7) >> +#define PM_LINKST_IN_L2 BIT(5) >> +#define PM_LINKST_IN_L1 BIT(4) >> + >> /* PARF_PCS_DEEMPH register fields */ >> #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, >> 16), x) >> #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, >> 8), x) >> @@ -737,6 +744,31 @@ static int qcom_pcie_post_init_2_4_0(struct >> qcom_pcie *pcie) >> return 0; >> } >> +static int qcom_pcie_debugfs_func_2_4_0(struct seq_file *s, void *data) >> +{ >> + struct qcom_pcie *pcie = (struct qcom_pcie *) >> dev_get_drvdata(s->private); >> + >> + seq_printf(s, "L0s transition count: %u\n", >> + readl_relaxed(pcie->parf + PM_LINKST_IN_L0S)); >> + >> + seq_printf(s, "L1 transition count: %u\n", >> + readl_relaxed(pcie->parf + PM_LINKST_IN_L1)); >> + >> + seq_printf(s, "L1.1 transition count: %u\n", >> + readl_relaxed(pcie->parf + PM_LINKST_IN_L1SUB)); >> + >> + seq_printf(s, "L2 transition count: %u\n", >> + readl_relaxed(pcie->parf + PM_LINKST_IN_L2)); >> + > > Using bitmask as register offset ? instead use PM_STTS and bitmask it ? Also, since its 1 bit, all are status and not count. Not sure, if you want it to limit this debug based on 'mhi' property being populated ? Regards, Sricharan
On Tue, Mar 14, 2023 at 04:25:29PM +0530, Sricharan Ramabadhran wrote: > > > On 3/14/2023 4:06 PM, Sricharan Ramabadhran wrote: > > > > > > On 3/10/2023 9:38 AM, Manivannan Sadhasivam wrote: > > > Qualcomm PCIe controllers of version v2.4.0 have debug registers in the > > > PARF region that count PCIe link transitions. Expose them over debugfs to > > > userspace to help debug the low power issues. > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > --- > > > drivers/pci/controller/dwc/pcie-qcom.c | 33 ++++++++++++++++++++++++++ > > > 1 file changed, 33 insertions(+) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c > > > b/drivers/pci/controller/dwc/pcie-qcom.c > > > index f99b7e7f3f73..0b41f007fa90 100644 > > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > > @@ -37,6 +37,7 @@ > > > /* PARF registers */ > > > #define PARF_SYS_CTRL 0x00 > > > #define PARF_PM_CTRL 0x20 > > > +#define PARF_PM_STTS 0x24 > > > #define PARF_PCS_DEEMPH 0x34 > > > #define PARF_PCS_SWING 0x38 > > > #define PARF_PHY_CTRL 0x40 > > > @@ -84,6 +85,12 @@ > > > /* PARF_PM_CTRL register fields */ > > > #define REQ_NOT_ENTR_L1 BIT(5) > > > +/* PARF_PM_STTS register fields */ > > > +#define PM_LINKST_IN_L1SUB BIT(8) > > > +#define PM_LINKST_IN_L0S BIT(7) > > > +#define PM_LINKST_IN_L2 BIT(5) > > > +#define PM_LINKST_IN_L1 BIT(4) > > > + > > > /* PARF_PCS_DEEMPH register fields */ > > > #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, > > > 16), x) > > > #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) > > > FIELD_PREP(GENMASK(13, 8), x) > > > @@ -737,6 +744,31 @@ static int qcom_pcie_post_init_2_4_0(struct > > > qcom_pcie *pcie) > > > return 0; > > > } > > > +static int qcom_pcie_debugfs_func_2_4_0(struct seq_file *s, void *data) > > > +{ > > > + struct qcom_pcie *pcie = (struct qcom_pcie *) > > > dev_get_drvdata(s->private); > > > + > > > + seq_printf(s, "L0s transition count: %u\n", > > > + readl_relaxed(pcie->parf + PM_LINKST_IN_L0S)); > > > + > > > + seq_printf(s, "L1 transition count: %u\n", > > > + readl_relaxed(pcie->parf + PM_LINKST_IN_L1)); > > > + > > > + seq_printf(s, "L1.1 transition count: %u\n", > > > + readl_relaxed(pcie->parf + PM_LINKST_IN_L1SUB)); > > > + > > > + seq_printf(s, "L2 transition count: %u\n", > > > + readl_relaxed(pcie->parf + PM_LINKST_IN_L2)); > > > + > > > > Using bitmask as register offset ? instead use PM_STTS and bitmask it ? > > Also, since its 1 bit, all are status and not count. > Not sure, if you want it to limit this debug based on 'mhi' property > being populated ? > Err... Look like I blindly copied the debugfs function from 2.7.0 :/ Sry, since these are all just 1 bit, we cannot use it for getting the count. So I'll drop this patch in next revision. Thanks, Mani > Regards, > Sricharan
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f99b7e7f3f73..0b41f007fa90 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -37,6 +37,7 @@ /* PARF registers */ #define PARF_SYS_CTRL 0x00 #define PARF_PM_CTRL 0x20 +#define PARF_PM_STTS 0x24 #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 @@ -84,6 +85,12 @@ /* PARF_PM_CTRL register fields */ #define REQ_NOT_ENTR_L1 BIT(5) +/* PARF_PM_STTS register fields */ +#define PM_LINKST_IN_L1SUB BIT(8) +#define PM_LINKST_IN_L0S BIT(7) +#define PM_LINKST_IN_L2 BIT(5) +#define PM_LINKST_IN_L1 BIT(4) + /* PARF_PCS_DEEMPH register fields */ #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) @@ -737,6 +744,31 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_debugfs_func_2_4_0(struct seq_file *s, void *data) +{ + struct qcom_pcie *pcie = (struct qcom_pcie *) dev_get_drvdata(s->private); + + seq_printf(s, "L0s transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L0S)); + + seq_printf(s, "L1 transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L1)); + + seq_printf(s, "L1.1 transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L1SUB)); + + seq_printf(s, "L2 transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L2)); + + return 0; +} + + +static void qcom_pcie_init_debugfs_2_4_0(struct qcom_pcie *pcie) +{ + qcom_pcie_init_debugfs(pcie, qcom_pcie_debugfs_func_2_4_0); +} + static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; @@ -1300,6 +1332,7 @@ static const struct qcom_pcie_ops ops_2_4_0 = { .post_init = qcom_pcie_post_init_2_4_0, .deinit = qcom_pcie_deinit_2_4_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .init_debugfs = qcom_pcie_init_debugfs_2_4_0, }; /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
Qualcomm PCIe controllers of version v2.4.0 have debug registers in the PARF region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)