From patchwork Wed Mar 15 06:42:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13175408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E344DC7618D for ; Wed, 15 Mar 2023 06:45:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231599AbjCOGpq (ORCPT ); Wed, 15 Mar 2023 02:45:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231544AbjCOGpV (ORCPT ); Wed, 15 Mar 2023 02:45:21 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7B2A410AF for ; Tue, 14 Mar 2023 23:44:43 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id y2so17751556pjg.3 for ; Tue, 14 Mar 2023 23:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678862656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=yU/LS6zv6HRSumZPPOqi4buo7Fv4Rr9rlsR73c7/CgYP4KYZB71Vl0RkNf4cXdwOlN 4UIfYXjHiN2QQcr/EI80z+dx4xbCg7ud7n2O/X1FTSuhZE278y0fsRwVlA21uNI/WR+4 MjlHhRi2DL4mSxEuD+alH6eS5ukMFXiGgPQ9jAwxY80v6RkbrqKVl9zXAhkSvZY/9jQT dFZlLogAvgXmbDk61hgnu0Fb03pr3uCM2tOUc3DjLzxt475fJwCM3FUpXKR71CWEt/Dm 2S+6OL/4sBRUGAvakBhJ/mj7fnbtgHtMQ3m70486Ifu9oVTOjErpj05crLGtrV2GVe6P UbOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678862656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=me818WqJeeCCeyiHQ+3QrOUwy0aKpzlwlLmDhk/4oL29UFi1ZYiBYHXUkzgNDXu3ww 86wERAgKR4t1IBhKQNePcxJmQnP/C/8+biXK/CTzrGFhi6ln1X3vH2/a7U+V/t969GTP FOvNJkH33s7veBaHvh0rJ/0sC8VRaOobcD7r3fymH133aWJBa/geAihBNh1zg30x33+V 9wI2ZR7qA4OafgXuWuu+rfhk1OMGXlXCjef1yXvUrX3Wm2lk9Q5scTcplemE/VDsM8xr OYdTDWPmXkqf5dnA1rImo2iCvcD92rwY3dCVXHTgb2D+E/J6nDZ9pS0vHYwCKoYKmcex aakg== X-Gm-Message-State: AO0yUKUTuPZU40/IRVfMtqEHuVTCORBGmWjSJBnoQhb/aGGiU4Rf1MKq aE8D15QVNA7h3X3OH9claoNi X-Google-Smtp-Source: AK7set+HyiYXAsfQAhco/yuZJyNEl0rLvwSpao4FzJMcJrCSzZMU3huLz703VVj5QdQjeAVo/x6bVA== X-Received: by 2002:a17:90a:bf15:b0:23d:2e22:17c9 with SMTP id c21-20020a17090abf1500b0023d2e2217c9mr5594518pjs.5.1678862656412; Tue, 14 Mar 2023 23:44:16 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.35]) by smtp.gmail.com with ESMTPSA id u4-20020a17090a6a8400b002367325203fsm550747pjj.50.2023.03.14.23.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 23:44:15 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 17/18] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes Date: Wed, 15 Mar 2023 12:12:54 +0530 Message-Id: <20230315064255.15591-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> References: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..eb87c3e5d2bc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1653,8 +1653,9 @@ pcie4: pcie@1c00000 { <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, - <0x0 0x30100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x30100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, @@ -1752,8 +1753,9 @@ pcie3b: pcie@1c08000 { <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, - <0x0 0x32100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x32100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, @@ -1849,8 +1851,9 @@ pcie3a: pcie@1c10000 { <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, - <0x0 0x34100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x34100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, @@ -1949,8 +1952,9 @@ pcie2b: pcie@1c18000 { <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, - <0x0 0x38100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x38100000 0x0 0x100000>, + <0x0 0x01c1b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, @@ -2046,8 +2050,9 @@ pcie2a: pcie@1c20000 { <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, - <0x0 0x3c100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,