From patchwork Tue Apr 4 08:24:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13199282 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B42FAC77B62 for ; Tue, 4 Apr 2023 08:25:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234217AbjDDIZX (ORCPT ); Tue, 4 Apr 2023 04:25:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234178AbjDDIZO (ORCPT ); Tue, 4 Apr 2023 04:25:14 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05E131BCE; Tue, 4 Apr 2023 01:25:13 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id eh3so127222137edb.11; Tue, 04 Apr 2023 01:25:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680596711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RW4xQc3ikP0AK8TIDBwhgtC3jzWZc1PY5oJEvurirtM=; b=BQSCnClFnlxwWlNN3DOSoyRfgI2NVmn+NdADPC/2aHdYSzkKKHUTthLZBipKUbLxCR PrbrL8Mh683vzUiBtIuApELulhpDYzAE8x80zypjk0+ZaS9xrbjHcewQwoHw2GydXfh4 ZLeljBSxSYlzbR3omrSk7/IwdNXMXy7eNs2wb0SFVknNsk63gHpo6/9LcK5s9PDrDLTi r7visnoeg8LIUkpMZ67/4hs71ss2XvzsesgKAewcLz9xcfTBeAHjxbazGV/M99lverDx QawVtzx9RFZQBTuLlDp3zeURb4e2JDDer6Fez0OgAqvO/ChrGhqskYpUVlink3iCmEjG xIXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680596711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RW4xQc3ikP0AK8TIDBwhgtC3jzWZc1PY5oJEvurirtM=; b=Km0fTGpOvhrLBgDsTnGgbpOF5I9V0VP6S8wtlKKZ8Ro3odGPR9YufhJd0A6uadhqLx 92J2kJc1Pikt6EVda7bg6LgjOZEk4JWbDGKZ4jjgaZ1lJvW7a7tVxmKqZCzXAIgy2QSZ Z6LKTiPU9p/L4xXb0bFT3OjqKuDSV0kPLAWgVClggWhxdF01VabeQb2NS0l/JGExNtf+ vgzJgewlAxcb6KEoUg0ku0qBH/3kOihf3Pe2yAE1kQ/cc5YW5NccgR4cqZZPgiXqKE9H rrJ+4xUhaYNQqn2xF2HXVQFqY7i01wbYbvLPJtdA9PaF5QKeLgwuKbU8gfMkOorasMeG YaZg== X-Gm-Message-State: AAQBX9fTVbb9zeQsXr0HZKt4NC4QqwsXQMVT5HPczJZo1GxhivJPQ+nB lX5qPV6j53HIj/ezOi7ToKo= X-Google-Smtp-Source: AKy350ZtH/tPJlarxTbHi8MVZ4f+XMBRlz6L67phf+7sEXOHB2MWF3l6wyRM7erwq8A1xjNY6hXS5g== X-Received: by 2002:a17:906:408e:b0:931:af6a:ad0f with SMTP id u14-20020a170906408e00b00931af6aad0fmr1328999ejj.76.1680596711395; Tue, 04 Apr 2023 01:25:11 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id s5-20020a170906454500b008e54ac90de1sm5640652ejq.74.2023.04.04.01.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 01:25:11 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: damien.lemoal@opensource.wdc.com, xxm@rock-chips.com, Rick Wertenbroek , Shawn Lin , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Johan Jonker , Brian Norris , Caleb Connolly , Corentin Labbe , Hugh Cole-Baker , Sascha Hauer , Judy Hsiao , Lin Huang , Arnaud Ferraris , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 05/11] arm64: dts: rockchip: Add dtsi entry for RK3399 PCIe endpoint core Date: Tue, 4 Apr 2023 10:24:18 +0200 Message-Id: <20230404082426.3880812-6-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230404082426.3880812-1-rick.wertenbroek@gmail.com> References: <20230404082426.3880812-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add dtsi entry for RK3399 PCIe endpoint core in the device tree. The status is "disabled" by default, so it will not be loaded unless explicitly chosen to. The RK3399 PCIe endpoit core should be enabled with the RK3399 PCIe root complex disabled because the RK3399 PCIe controller can only work one mode at the time, either in "root complex" mode or in "endpoint" mode. Signed-off-by: Rick Wertenbroek --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 928948e7c7bb..c16c6176cffc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -265,6 +265,33 @@ pcie0_intc: interrupt-controller { }; }; + pcie0_ep: pcie-ep@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + rockchip,max-outbound-regions = <32>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + reg = <0x0 0xfd000000 0x0 0x1000000>, + <0x0 0xfa000000 0x0 0x2000000>; + reg-names = "apb-base", "mem-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + status = "disabled"; + }; + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>;