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Thu, 11 May 2023 23:27:54 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 12 May 2023 01:27:51 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , Thippeswamy Havalige Subject: [PATCH v2 2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Date: Fri, 12 May 2023 11:57:24 +0530 Message-ID: <20230512062725.1208385-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230512062725.1208385-1-thippeswamy.havalige@amd.com> References: <20230512062725.1208385-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT056:EE_|PH7PR12MB5619:EE_ X-MS-Office365-Filtering-Correlation-Id: af417cf1-9431-4590-0184-08db52b205c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VZNv13vwZiIgw8cU4NAUkLGlXz9kTseL1kGG3PuYwha71+HeVbxxXU8rBQfvq3XZkL+MXJz1HkQq4HpBjQJlymsuTd7+8dl8CT+MpPAifwu1S43t9HwAPp+8S0XcI1/P9OfZHeQ1A2ZjTsO3J/RusuzLy6d1vVSMb6j4nNIEVZmq/dXUKZDRVNbUQd7IgDp3y7CWCIiI9ZrlaE9ESxLAePsCeyxXXL8pACXnkcWEzlyyOpnnkqObxNf/MTo6UYg8ROke/GbjL78SdH84AvCiAdI4p9aGRnZ3t/cZM0xVdzC76db6pya0fJT7YOuwNbNSRtTQnJ+OHbDeYJnxCPxcSJyO7DOQlMc1nb7rGclQxkpVnv3QWbcxKbLMAaOuVb7360puxLsG5Za6dklTd9+lWJabFqzINm+G3VLXx4fKtSp62kKaInMciaPAx+7q6wWxz9sxPRNYSOYle4aEmq6b+aMw9KPeKsf8gMyMgcjiO0FdGHrU4O3fnXcfyo4mPYIEc+2gGQjU0QZAMCGBLewyaf5A4tiFvesVIJXvZP3aCyKEoAAQIYuj55Y9OUFdNcOpxzr/s4SsKIRzZra+XghYWJ1I7kjXI4Qb2FkE5eMvD9UlQ3dT6bLnU7YRf+lTJEnV5Q84SKQCH0c/oYpgAgm/yqpROKcrhiSFYRLFyY/BVZHG20ycM7vKuUOhpGFV8SNbCXD4rz//UebkmPRQK8urC3OEFNsMArtbCWU7IWi4SZ2qNs+vzvcrRq3a0ctbR7n8Y2r/9CbpIoHl2vEaL8ifJnDD+fxjZeWj5XjIgQQtaXc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199021)(46966006)(40470700004)(36840700001)(81166007)(44832011)(478600001)(1076003)(26005)(316002)(356005)(47076005)(36860700001)(41300700001)(70586007)(426003)(336012)(70206006)(4326008)(54906003)(110136005)(82740400003)(966005)(2616005)(8676002)(86362001)(6666004)(8936002)(82310400005)(2906002)(186003)(36756003)(40460700003)(40480700001)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 06:27:55.6169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af417cf1-9431-4590-0184-08db52b205c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5619 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add YAML dtschemas of Xilinx XDMA Soft IP PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml new file mode 100644 index 0000000..e3a1ef1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XDMA PL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,xdma-host-3.0 + + reg: + maxItems: 1 + + ranges: + items: + - description: | + ranges for the PCI memory regions (I/O space region is not + supported by hardware) + + interrupts: + items: + - description: interrupt asserted when miscellaneous interrupt is received. + - description: msi0 interrupt asserted when an MSI is received. + - description: msi1 interrupt asserted when an MSI is received. + + interrupt-names: + items: + - const: misc + - const: msi0 + - const: msi1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - interrupt-map-mask + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@a0000000 { + compatible = "xlnx,xdma-host-3.00"; + reg = <0x0 0xa0000000 0x0 0x10000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = , , + ; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>, + <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>; + pcie_intc_0: interrupt-controller { + #address-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + }; + };