From patchwork Wed Jun 14 15:55:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13280175 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4B52EB64D9 for ; Wed, 14 Jun 2023 15:56:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236300AbjFNP4L (ORCPT ); Wed, 14 Jun 2023 11:56:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236766AbjFNP4I (ORCPT ); Wed, 14 Jun 2023 11:56:08 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 237691BC for ; Wed, 14 Jun 2023 08:56:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686758167; x=1718294167; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iQVdQ5/Fd7A+l93rxa4YuqFXIveaFWB1LxC6Y87vXmk=; b=L65XuDxuapsBBoDyiwgz9CyggiFV7lt+r1Z55xGTSDoJSx17GDAr63f4 0MHiLitLwZzADWRdwVavINdO8zFQjsZ4rkWC9JcSNLEeqn1KLKGjliCon hfC5ZPF3nZZdE7d2X9hZ6SODennzFAQns54ROmWfth5U+dTlJkG+0vj43 N67mAVLA9oQthX2QJNfxE3lAnTefdrOSEFsC5L4rt8Cv2ER5vvCjFp+FC e1vNvHY4vP8XCKdXffMnHEoG2voNNePCFmakdW8cjNtMHjtmExuu6w4F2 lggxOvSURXxgMcatR4G4Tz1xa9qiaGbiPgmikztjDP/OWd+/hzq09E49p Q==; X-IronPort-AV: E=Sophos;i="6.00,242,1681196400"; d="scan'208";a="156969572" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jun 2023 08:56:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 14 Jun 2023 08:56:02 -0700 Received: from daire-X570.emdalo.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 14 Jun 2023 08:56:01 -0700 From: To: , , , , , , CC: Daire McNamara Subject: [PATCH v1 1/8] PCI: microchip: Correct the DED and SEC interrupt bit offsets Date: Wed, 14 Jun 2023 16:55:49 +0100 Message-ID: <20230614155556.4095526-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614155556.4095526-1-daire.mcnamara@microchip.com> References: <20230614155556.4095526-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Daire McNamara The SEC and DED interrupt bits were the wrong way round so the SEC interrupt handler attempted to mask, unmask, and clear the DED interrupt and vice versa. Correct the bit offsets so each interrupt handler operates properly. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver") Signed-off-by: Daire McNamara Reviewed-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 5e710e485464..dd5245904c87 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -167,12 +167,12 @@ #define EVENT_PCIE_DLUP_EXIT 2 #define EVENT_SEC_TX_RAM_SEC_ERR 3 #define EVENT_SEC_RX_RAM_SEC_ERR 4 -#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5 -#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6 +#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 +#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 #define EVENT_DED_TX_RAM_DED_ERR 7 #define EVENT_DED_RX_RAM_DED_ERR 8 -#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9 -#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10 +#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 +#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13