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Thu, 10 Aug 2023 07:20:08 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 10 Aug 2023 07:20:05 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Date: Thu, 10 Aug 2023 17:49:59 +0530 Message-ID: <20230810122002.133531-1-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E4:EE_|DS0PR12MB7947:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f5f88e0-e98d-4cef-4653-08db999c2bc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n90eGvbbkVsnsxaNJGVDe4+zj6qkzCzPZMhdb/PH48qM+xR9jAapzzm0ojQN01szn7lrb6l+RfXqJDk6nu/xSlu30E8qnmOLAd8BCgAatJ0TR8qE6XioSj8hqGJDF3sGWOw6aZ7TqcGGFq91uo6CWZNYJT8SY1TY8CWqCmfblW8ZTNBNtcFpnxyJD5zVyRYoli70UlsNh8hhZY7lnKtuT5Fde+ihPxgNDftvlOfqC2vvKuFxPVPZWDiL9BMMelo3tduVvpO37CxLzZfwpLYTE5x2FH9FZkEdwoQDT4NolYjvKfcp6Lj6D5eafSTlVKTRql8UPh06gMIAGgasdhdIYXnaoNRA/BtX8BnAJItuEHAIteECZKNSlJR7vvfN1fqMJwvT3ih1SxFPJfO2WAssr0wILB+KLGtFjzQFxSgfMCZJcxI2u4gjnqjcOyMHsPmktEdPKBduwM++tdnAePsPvuCcmq3I0E53WUsGxIAvlciC8M46XysxI8xSXpb5zbhgJLeR96mz+KscO85g9O6eD8r8WMRVrzBSq4MkI5Cs4XrdAJpE7IHXIPJpBemlh4yb8WQNw4gi6nLSLR7AfKuhaKKQCmOFQSKegKp+qsafBD3vAK9OsFXehg32NY2RHshwW58hsybmJBZsjB8AE3zGMClkjM024DvvYwNj8s6ajoH+++gLz3u/KPor1rcoi85qIErwLjeHIx+DyaM5SglnQ8gesTqNQ7DYbMChW8mrmoeDbNtf0vSn6sXr2gUHiYbIEoo/V0mmXreHWZggM7i0vA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(396003)(376002)(39860400002)(82310400008)(451199021)(1800799006)(186006)(40470700004)(46966006)(36840700001)(26005)(5660300002)(1076003)(8936002)(8676002)(41300700001)(40460700003)(82740400003)(36860700001)(36756003)(47076005)(2906002)(426003)(83380400001)(15650500001)(356005)(81166007)(2616005)(86362001)(44832011)(336012)(70206006)(4326008)(70586007)(6666004)(54906003)(110136005)(478600001)(40480700001)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2023 12:20:22.9307 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f5f88e0-e98d-4cef-4653-08db999c2bc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7947 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else