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Thu, 10 Aug 2023 07:20:19 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 10 Aug 2023 07:20:16 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v3 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 10 Aug 2023 17:50:02 +0530 Message-ID: <20230810122002.133531-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810122002.133531-1-thippeswamy.havalige@amd.com> References: <20230810122002.133531-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT103:EE_|SN7PR12MB7369:EE_ X-MS-Office365-Filtering-Correlation-Id: 24a4a6bb-4661-4109-bf4f-08db999c2fe5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 67zpsX3/Z3mnXSkhrPRdOobXGT6Uu3j2BbnJMQWxEIVZSSR1rdGRTTkw4FlgfGhPZFwZGH7zxwlljKdhhElLU63898ON4jWIpNjiPvgzj4QD8tfsg0zN5/UshPYnvtATgTWZUGEtIajfWs+uBH51quCdnoVQaOEChrQv7i/d3ONgw6RktGMj70Ojp6+DhqnmSRnF3I8izbXZ6VmjqTLX/mwjR4wWPCixyBqU62/bsyuMTa5w/qdW0O3Y0ltcCNceMuQPgMWgv8TqGcceiYSoM+DJAWE7HSO8h8t7WhtOKtVJMTVp8VG+c+SdoLuoeEzs2XZAS/r1AA9/dzHgO/FnnCmQDMQS2cbywuKTKOrgryboSLtJ4t5AazFq1fpoTDGqDT0hdhM/QczI3+9Ct8SxEo5+KCIMun/aTr+GG1Jmbr0c2VCcBw953OcU6hezKgzVUTo7YuFUx1A0k7gBlsCsqXrwj6cJXUli+dl6KO8ualwhw+vQPr0oz/d8eh7GJ5+tlIiy86zYXHvCU4/d5SQA203NizW3VmhRFEzXbYczfu6bI6zI92l9bGRlkI8Muh7Fjzoz9Kf3nMHqhflOCpmPnTUPOhUkY7C2M/Ou6EGje+/HZQFI9E1coBSIsDmz37wzvFkPCvJ1sK9nYIGDs0DZ51T4aRNpjDlGsKlXcVSdv00L2s7cNEMvnUzD04Kz8Gpx9+uv0P9nCMJMbVN0pdZgTnHFGRJG2uqhxuFkclNnqDbHAq6IJhA8keXXwrraD2LdeVq7PeIdAuW0Rbpl6yfnEw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(39860400002)(396003)(346002)(186006)(451199021)(1800799006)(82310400008)(46966006)(36840700001)(40470700004)(316002)(81166007)(356005)(70586007)(70206006)(4326008)(82740400003)(41300700001)(8676002)(8936002)(110136005)(54906003)(36860700001)(47076005)(5660300002)(83380400001)(336012)(40480700001)(2616005)(478600001)(426003)(86362001)(44832011)(26005)(40460700003)(1076003)(36756003)(2906002)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2023 12:20:30.0278 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24a4a6bb-4661-4109-bf4f-08db999c2fe5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7369 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v3: - Remove unnecessary period at end of subject line. changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..b51501921d3b 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_VALUE_DEFAULT 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) {