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Thu, 17 Aug 2023 07:10:51 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 17 Aug 2023 07:10:48 -0500 From: Thippeswamy Havalige To: , , CC: , , , , , , , "Thippeswamy Havalige" , Bharat Kumar Gogada Subject: [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Date: Thu, 17 Aug 2023 17:40:40 +0530 Message-ID: <20230817121044.8176-1-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|MN6PR12MB8471:EE_ X-MS-Office365-Filtering-Correlation-Id: cedc233e-fff9-40d1-e8da-08db9f1b0040 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bL2Pl2AZ4U0IOcMBPog231G/fHJ7AZKiuJALzoSndtFNGspFK/C9U16KXJYC0zikguWWNXqWQ9jN1V4vaGkN6Dpp7BlrdC7F8/SQk1Y75qptJxD7KAbAmTJdxljcp60iejV9Fxwc5l5r4AXmOMcpGH/WzSz/FlPWITgX9PWKU7g69LgN//+mXV3PPuv1RMCUG3JJ3l4JV0b8PEaFhQKIclb9z3nMTUqmwS85s6t1tgHAYAWWzsEDgFZvAcX58BWVo1osTmBZ+AyHWyuzItjRsKJ3GXKucqq3MMzsC01t5OXi+j7UIMbnASBfAIwJ51lLDx5Xcr5ZhY+qA/bChNNcxAWkHz/C4mEAyYaSM463zfWISooTO8f3tyu56IY1kJbDuhtD96+89IpRJVINKPPrW0jxtjZL8N4pdQO7iLLXWS1tmj/7LoDIN0CRCna8OOAEF4TZhvc45jHqjyJmGUAyanokghrqE6JkeAdGVEveHt0Ja2INfHTUroKqJfjRBZwP1/8TxbwByDLRLz3UX+DkK+6/TUC3TdlK8AL42/yGivN6HY4B/vvWzgGRAwL0X+2POn23do16G7qmn9Q4NBaVSDwkxTuavqEcGWQ03x02UaTL5wgD3OHSN7PDy2b+vj0/Eza8WcZ3aK7dlI78Xr/a/jth2p1D/CRQhv7sMT9fEzPk446UoqOmdoSTwVeBSgb0Lah3sl/AIfo5Rp0rLJyNJsySWlE5TC4PAJKiZqIUAwYyQHa99FUD5h62wX71nsh5FGhDL2ydjHltmnO1XjGQbIBQV50L9p38vMNJ+yKkBKY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(136003)(376002)(1800799009)(451199024)(186009)(82310400011)(46966006)(40470700004)(36840700001)(316002)(54906003)(82740400003)(356005)(110136005)(81166007)(70586007)(70206006)(5660300002)(41300700001)(36860700001)(44832011)(47076005)(4326008)(8936002)(8676002)(26005)(40460700003)(2906002)(15650500001)(83380400001)(40480700001)(336012)(478600001)(426003)(7416002)(86362001)(36756003)(6666004)(1076003)(2616005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 12:10:51.9775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cedc233e-fff9-40d1-e8da-08db9f1b0040 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8471 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else