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Thu, 17 Aug 2023 05:11:05 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 17 Aug 2023 07:11:02 -0500 From: Thippeswamy Havalige To: , , CC: , , , , , , , "Thippeswamy Havalige" Subject: [PATCH v5 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 17 Aug 2023 17:40:44 +0530 Message-ID: <20230817121044.8176-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230817121044.8176-1-thippeswamy.havalige@amd.com> References: <20230817121044.8176-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT094:EE_|DM4PR12MB5167:EE_ X-MS-Office365-Filtering-Correlation-Id: da6d1862-542f-4f54-4238-08db9f1b08c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7bniovtrBnps5m6sIOUoMpcaZqD0CthDUgJ1eeLxw1WDEMLj5wMxG0yjiW2IfTQDZbFewt55c4HavytyvQLwPaggBzXfIEnqISQ1YLN+sq0ffXRD6khsLyafjMDq7jEReB/BzzKGHNshv8bkQYYyN9kACuC81MqD6GkOSQ/VMr27jy1Q3KFA7f2e3nDbfd7GBJKE5+tVhcb5sk1dTswyZ+CPd1BbglrGZLV/yRX/FfRKI6gsAPOsO5o54NI2vNkYLg7MWIuizzPiXkbGfdEEWGbO3uWYn9/D7Emtje7Ofmy4z22/e7kFVJ9eiWG/b6F+SFqYSFl6kpC9lropOqk7YZ4Bn8AUxi+wuHaMpQPBfPcjbTg1XbEsMTn63OBmzgFSkbeRKxT3ACxb/hHPGSm2Za/cP7XWpCkmng7u0R5W9yGpGKBySOHzMJeGOT8pZWOP1ynDLQXTAUsIKv1FGcFDUP8huIeUMhOUkZz/h/SjcsO5+d4ldWgROwy5UpBge66h/g6Oh6dUDRxLN1SzwN+8K9K7oyUV5jn9evlwAPhpoIJbzBmzOhRiKGHHS9T5GuWyBU6Z5RCCCQ+qam3suRkUR1R2w5pjMzj3b3CCOfZXdhIeix8Kwh/QE3mpcP6An58zY1OHGAugrxmXnFF3rrq3Sgfug2dWCQWcOPg2PSNLC1fIaXtmcbtiX355c3ztaJZc3Fjgv1g5WhY1X4rpR66cBUbYEbRr7E7yotVEZ82CIZX059GfuSWn2HvxbIxoLqm0kJVA129XDUB6drR/Bu71Y76+M1Ce0iMFXrZLAjniXWo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199024)(1800799009)(82310400011)(186009)(40470700004)(36840700001)(46966006)(86362001)(36756003)(82740400003)(356005)(81166007)(40480700001)(5660300002)(44832011)(2616005)(110136005)(70206006)(70586007)(478600001)(316002)(6666004)(54906003)(26005)(1076003)(4326008)(8936002)(41300700001)(8676002)(40460700003)(36860700001)(336012)(7416002)(2906002)(426003)(47076005)(4744005)(83380400001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 12:11:06.2223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da6d1862-542f-4f54-4238-08db9f1b08c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5167 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)