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Wed, 30 Aug 2023 04:07:28 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Wed, 30 Aug 2023 04:07:25 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , , Thippeswamy Havalige Subject: [PATCH v7 1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Date: Wed, 30 Aug 2023 14:37:05 +0530 Message-ID: <20230830090707.278136-2-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230830090707.278136-1-thippeswamy.havalige@amd.com> References: <20230830090707.278136-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|BL1PR12MB5779:EE_ X-MS-Office365-Filtering-Correlation-Id: cdf51cb5-0762-4894-dd2b-08dba93889c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: if/in1Xva2ns+EzV52iilHpj2fxOlI0SLINiCeqsMsEY44Z7zKLKBydn9GvgnQDEmS6lDYTAH/LzgmZ5aO4FbUVfIvLjhxiEALE1uziL9JxoYr46PR3KLJ3mSDWRkP1I171i5RUfKFm7e82h1TfZdSzZiWj0eijOYJAmZ+1NnOmj3ejv77TMykt+bqGkTDEdBVNALPu/A//cbqhvgF0yftMHMW1MSynwzyFDdDLtDoJ1w6zJ7ekCmot5pGDDtWAjCnTzGlMnq3oFX9qj9Zn3oX/Vn/1jaLHQ/414iMmGmJkskmf4JyL5qqHxfxhQWsgJoU3MzyfeZxKVWka6opYMCeoAspS6VqKJ6Gjy0M+wi1W2WDF2ZVA3GyMxzITXkedF7DQCBkk8GA5Kg/otufoXr3AwlfzdH76YQZoOiTMbKGzLFlzdLxhUN434yfZdKcciAIfy6gNMAD5xxMsmOZzVLYzbWPlSz2mtaL97oUtdALvMDw3gl5gqSmjmnyg/ekyzd0DtIBglbd+hLABvJlHnAUrKDS1GJUZTj6jW1Jv61DO+onl6VliiwV/xQaVbkngwChxzUUCJFhRwuK917eG5qGFE8KAtUbqAu2bcjv91b87JIkoqAwxtyKVNK5r9TX/d6ueMhnVqQDhXcsxtVjlkxfQMRNlKyfK0r7KHXGGgSrhfjbB6oyAI0Wlb25nSLQQTqnfFGFoosviej2/2T8/6AagIwv+cTX3zCbcAtLK6Q53w/UgpLRvYHT9cVFR0PzIqbpBueKvkIkYHJC4eOHAJu/zpq3JI5GQ4NrqXgBzGwHA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(376002)(136003)(82310400011)(186009)(1800799009)(451199024)(36840700001)(46966006)(40470700004)(82740400003)(6666004)(4326008)(47076005)(40460700003)(86362001)(40480700001)(36756003)(356005)(81166007)(2906002)(36860700001)(426003)(83380400001)(336012)(1076003)(26005)(478600001)(110136005)(8676002)(41300700001)(70586007)(44832011)(8936002)(5660300002)(70206006)(54906003)(316002)(2616005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Aug 2023 09:07:29.6944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdf51cb5-0762-4894-dd2b-08dba93889c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5779 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename Xilinx interrupt bit definitions so they are not CPM-specific. Move the definitions to pcie-xilinx-common.h where they can be shared between pcie-xilinx-cpm and the new xilinx-xdma driver. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v7: - None changes in v6: - subject line and commit message changes in v5: - None changes in v4: - None changes in v3: - changed licensing year to 2023 --- drivers/pci/controller/pcie-xilinx-common.h | 30 +++++++++++++++++++++++ drivers/pci/controller/pcie-xilinx-cpm.c | 38 ++++++----------------------- 2 files changed, 37 insertions(+), 31 deletions(-) create mode 100644 drivers/pci/controller/pcie-xilinx-common.h diff --git a/drivers/pci/controller/pcie-xilinx-common.h b/drivers/pci/controller/pcie-xilinx-common.h new file mode 100644 index 0000000..e97d272 --- /dev/null +++ b/drivers/pci/controller/pcie-xilinx-common.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2023, Xilinx, Inc. + */ + +#include +#include +#include + +/* Interrupt registers definitions */ +#define XILINX_PCIE_INTR_LINK_DOWN 0 +#define XILINX_PCIE_INTR_HOT_RESET 3 +#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT 4 +#define XILINX_PCIE_INTR_CFG_TIMEOUT 8 +#define XILINX_PCIE_INTR_CORRECTABLE 9 +#define XILINX_PCIE_INTR_NONFATAL 10 +#define XILINX_PCIE_INTR_FATAL 11 +#define XILINX_PCIE_INTR_CFG_ERR_POISON 12 +#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD 15 +#define XILINX_PCIE_INTR_INTX 16 +#define XILINX_PCIE_INTR_PM_PME_RCVD 17 +#define XILINX_PCIE_INTR_SLV_UNSUPP 20 +#define XILINX_PCIE_INTR_SLV_UNEXP 21 +#define XILINX_PCIE_INTR_SLV_COMPL 22 +#define XILINX_PCIE_INTR_SLV_ERRP 23 +#define XILINX_PCIE_INTR_SLV_CMPABT 24 +#define XILINX_PCIE_INTR_SLV_ILLBUR 25 +#define XILINX_PCIE_INTR_MST_DECERR 26 +#define XILINX_PCIE_INTR_MST_SLVERR 27 +#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT 28 diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index 4a787a9..a0f5e1d 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -16,11 +16,9 @@ #include #include #include -#include -#include -#include #include "../pci.h" +#include "pcie-xilinx-common.h" /* Register definitions */ #define XILINX_CPM_PCIE_REG_IDR 0x00000E10 @@ -38,29 +36,7 @@ #define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 #define XILINX_CPM_PCIE_IR_LOCAL BIT(0) -/* Interrupt registers definitions */ -#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0 -#define XILINX_CPM_PCIE_INTR_HOT_RESET 3 -#define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT 4 -#define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8 -#define XILINX_CPM_PCIE_INTR_CORRECTABLE 9 -#define XILINX_CPM_PCIE_INTR_NONFATAL 10 -#define XILINX_CPM_PCIE_INTR_FATAL 11 -#define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON 12 -#define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD 15 -#define XILINX_CPM_PCIE_INTR_INTX 16 -#define XILINX_CPM_PCIE_INTR_PM_PME_RCVD 17 -#define XILINX_CPM_PCIE_INTR_SLV_UNSUPP 20 -#define XILINX_CPM_PCIE_INTR_SLV_UNEXP 21 -#define XILINX_CPM_PCIE_INTR_SLV_COMPL 22 -#define XILINX_CPM_PCIE_INTR_SLV_ERRP 23 -#define XILINX_CPM_PCIE_INTR_SLV_CMPABT 24 -#define XILINX_CPM_PCIE_INTR_SLV_ILLBUR 25 -#define XILINX_CPM_PCIE_INTR_MST_DECERR 26 -#define XILINX_CPM_PCIE_INTR_MST_SLVERR 27 -#define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT 28 - -#define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x) +#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) #define XILINX_CPM_PCIE_IMR_ALL_MASK \ ( \ @@ -323,7 +299,7 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) } #define _IC(x, s) \ - [XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s } + [XILINX_PCIE_INTR_ ## x] = { __stringify(x), s } static const struct { const char *sym; @@ -359,9 +335,9 @@ static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id) d = irq_domain_get_irq_data(port->cpm_domain, irq); switch (d->hwirq) { - case XILINX_CPM_PCIE_INTR_CORRECTABLE: - case XILINX_CPM_PCIE_INTR_NONFATAL: - case XILINX_CPM_PCIE_INTR_FATAL: + case XILINX_PCIE_INTR_CORRECTABLE: + case XILINX_PCIE_INTR_NONFATAL: + case XILINX_PCIE_INTR_FATAL: cpm_pcie_clear_err_interrupts(port); fallthrough; @@ -466,7 +442,7 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port) } port->intx_irq = irq_create_mapping(port->cpm_domain, - XILINX_CPM_PCIE_INTR_INTX); + XILINX_PCIE_INTR_INTX); if (!port->intx_irq) { dev_err(dev, "Failed to map INTx interrupt\n"); return -ENXIO;