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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id c20-20020a056512325400b00507a387c4c4sm2180875lfr.229.2023.10.24.08.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:11:30 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id AFE691662; Tue, 24 Oct 2023 17:11:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160289; bh=L8JeOW9o9OlpyYp8SHB1xCbEeYmEJRvMKzVVwI04Dng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aNxrrkeMHEtEgkynoWTaqcE2AIWGnjuVlH6IbE589WRsZwdnrVf2oAE02HcA1RDvw jCfmtmT4/PMATU0zGar97eNFv4JIDcNvBlZ90261mvazUnBOnp6yS8mf1kDsYGQFAY GUKu195nvUKbRD0V+r8kbSos59X0H+wh+4JIFY48= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 6DD0214DB; Tue, 24 Oct 2023 17:10:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160244; bh=L8JeOW9o9OlpyYp8SHB1xCbEeYmEJRvMKzVVwI04Dng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uPFkoJhQzCTotouNSHQ5d5yXqQtgVNvrxssQNIiRGjZljqNeSck3cOMf+Lqe98O4F DFpvOEt+sQYUASd80WbXc+0bVXhId8ouznlvWlOUafB+CNUKeXDSWddDj12DKJyNXn 4jYl42Aiwaf8K2+7KgAeZClh7mrFfXknuXjdwWro= From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: Damien Le Moal , Sebastian Reichel , Niklas Cassel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 1/4] dt-bindings: PCI: dwc: rockchip: Add atu property Date: Tue, 24 Oct 2023 17:10:08 +0200 Message-ID: <20231024151014.240695-2-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Niklas Cassel Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml using: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# and snps,dw-pcie.yaml does have the atu property defined, in order to be able to use this property, while still making sure 'make CHECK_DTBS=y' pass, we need to add this property to rockchip-dw-pcie.yaml. Signed-off-by: Niklas Cassel --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 1ae8dcfa072c..229f8608c535 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -29,16 +29,20 @@ properties: - const: rockchip,rk3568-pcie reg: + minItems: 3 items: - description: Data Bus Interface (DBI) registers - description: Rockchip designed configuration registers - description: Config registers + - description: iATU registers reg-names: + minItems: 3 items: - const: dbi - const: apb - const: config + - const: atu clocks: minItems: 5