From patchwork Tue Nov 28 13:22:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13471140 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.b="PhcWpGng"; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.b="e+F6WINF" Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55FFEDA for ; Tue, 28 Nov 2023 05:23:53 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-507a98517f3so7356788e87.0 for ; Tue, 28 Nov 2023 05:23:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701177831; x=1701782631; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature:dkim-signature:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GBP9+ANTd+YeoKcJdvljTdpjHWIRh3Hzh1C2WywAX6M=; b=uLi18yyoFRK7FVUmAziM9rfAozGSA8PSdVHoIwFRdcoIXmJgsaQ/Ia1LknyJpE81UI kHn6S9z3vttp2KoeGpCJoo8s/G7LAJy2uU8DDg+b0G+nNhaXlfFjOud0lRt0x3S6W+8i aEvS0ldHY9sUmgvmZE3inQPvpi7BK0Z5rTflwFQ4OiyYo7JhDuXuw0o0NPBAXGtetwmq 8ZlDK0kMQC1SA4+hJbHbJFZcvkZnvdIK8D8JE/0Ddxfg/8UeZzBNe6kkJj9fu/74kwSW Vd36Kvxa+Lqo/ZSBRaRtQijp4fRUksU4qvNrj8SMp8Og0/Ryc4jumME+qY8hEkgcfnYY yo3g== X-Gm-Message-State: AOJu0YxoNpxYVaFvbgNIvX4NNJEg0cadvANKxaXfsEhRUi5qBEJB0rkH nHEduxCdb6L1gTSJ0rdRsV7h6kMfX7aZ42mZ X-Google-Smtp-Source: AGHT+IF5wv12ufUx+xWJWt8k6hNJkP+AYQNgUlmB5VfzR2E6/qUQb4gfBE4XkKcarw5CbzoHoFD0UA== X-Received: by 2002:a05:6512:10ca:b0:50b:b00b:e3ef with SMTP id k10-20020a05651210ca00b0050bb00be3efmr5875051lfg.62.1701177831496; Tue, 28 Nov 2023 05:23:51 -0800 (PST) Received: from flawful.org (c-55f5e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.245.85]) by smtp.gmail.com with ESMTPSA id c5-20020a056512324500b0050bc194d414sm23473lfr.303.2023.11.28.05.23.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 05:23:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1701177829; bh=e8b9fnxitWkWXRKnpPA0xPmyNbp8/i00cz0k+pMYsYY=; h=From:To:Cc:Subject:Date:From; b=PhcWpGngiVr9k/pKFETuPulU4Xw+BEF4rhpNrKsTPWyA2euoSvpr6OJ2vl1zMpn9X qvFa7JsMgf45efr55qoUXsL71BrXpncrN6JuE+iFtx4b0CvNfjvv7ONdX8oF6PB4LG MY8OVf/as2ZPTfPDnrKp8Nf+K2om4gDpaQw21haM= Received: by flawful.org (Postfix, from userid 112) id CE4CAC7E; Tue, 28 Nov 2023 14:23:47 +0100 (CET) X-Spam-Level: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1701177803; bh=e8b9fnxitWkWXRKnpPA0xPmyNbp8/i00cz0k+pMYsYY=; h=From:To:Cc:Subject:Date:From; b=e+F6WINFMfpxgoTfFvr+d3wQUfBdnMgKRkQI/0gAeDbhBVd4UnV1/Oc7l9D9b5pq9 RWw+7CaBfs57yKXtnmAYqG/ugMJj6zAaj7l7sfAsFldi0BcDREFSiyprLAWhQRBdRm UYqJC4F6oIQdsFelaAASeSDXcLMrTwKD/B0YkL+Y= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 39130A7F; Tue, 28 Nov 2023 14:23:20 +0100 (CET) From: Niklas Cassel To: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2] PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support Date: Tue, 28 Nov 2023 14:22:30 +0100 Message-ID: <20231128132231.2221614-1-nks@flawful.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Niklas Cassel Commit 6f5e193bfb55 ("PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address") modified dw_pcie_ep_raise_msix_irq() to support iATUs which require a specific alignment. However, this support cannot have been properly tested. The whole point is for the iATU to map an address that is aligned, using dw_pcie_ep_map_addr(), and then let the writel() write to ep->msi_mem + aligned_offset. Thus, modify the address that is mapped such that it is aligned. With this change, dw_pcie_ep_raise_msix_irq() matches the logic in dw_pcie_ep_raise_msi_irq(). Cc: Kishon Vijay Abraham I Fixes: 6f5e193bfb55 ("PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address") Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam --- Changes since v1: -Clarified commit message. -Add a working email for Kishon to CC. drivers/pci/controller/dwc/pcie-designware-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f6207989fc6a..bc94d7f39535 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -615,6 +615,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, } aligned_offset = msg_addr & (epc->mem->window.page_size - 1); + msg_addr &= ~aligned_offset; ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret)