| Message ID | 20231211091543.735903-1-LeoLiu-oc@zhaoxin.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] PCI: Extend PCI root port device IDs for Zhaoxin platforms | expand |
On Mon, Dec 11, 2023 at 05:15:43PM +0800, LeoLiu-oc wrote: > From: LeoLiuoc <LeoLiu-oc@zhaoxin.com> > > Add more PCI root port device IDs to the > pci_quirk_zhaoxin_pcie_ports_acs() for some new Zhaoxin platforms. > > v1 -> v2: > 1. Add a note to indicate future Zhaoxin devices will implement ACS > Capability based on the PCIe Spec. > 2. Includes DID of more Zhaoxin devices that have not yet implemented ACS > Capability. > > Signed-off-by: LeoLiuoc <LeoLiu-oc@zhaoxin.com> Applied as below to pci/virtualization for v6.8, thanks! This extends 299bd044a6f3 ("PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports"), so I made the subject similar to that, added a Fixes: line for it, and added a stable tag. > --- > drivers/pci/quirks.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index ea476252280a..f4546590d9e3 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -4706,10 +4706,14 @@ static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) > (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) > return -ENOTTY; > > + /* > + * Future Zhaoxin Root Ports and Switch Downstream Ports will implement ACS > + * capability in accordance with the PCIe Spec. > + */ > switch (dev->device) { > case 0x0710 ... 0x071e: > case 0x0721: > - case 0x0723 ... 0x0732: > + case 0x0723 ... 0x0752: > return pci_acs_ctrl_enabled(acs_flags, > PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); > } > commit e367e3c765f5 ("PCI: Add ACS quirk for more Zhaoxin Root Ports") Author: LeoLiuoc <LeoLiu-oc@zhaoxin.com> Date: Mon Dec 11 17:15:43 2023 +0800 PCI: Add ACS quirk for more Zhaoxin Root Ports Add more Root Port Device IDs to pci_quirk_zhaoxin_pcie_ports_acs() for some new Zhaoxin platforms. Fixes: 299bd044a6f3 ("PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports") Link: https://lore.kernel.org/r/20231211091543.735903-1-LeoLiu-oc@zhaoxin.com Signed-off-by: LeoLiuoc <LeoLiu-oc@zhaoxin.com> [bhelgaas: update subject, drop changelog, add Fixes, add stable tag, fix whitespace, wrap code comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: <stable@vger.kernel.org> # 5.7 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ea476252280a..d55a3ffae4b8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4699,17 +4699,21 @@ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) * But the implementation could block peer-to-peer transactions between them * and provide ACS-like functionality. */ -static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) +static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) { if (!pci_is_pcie(dev) || ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) return -ENOTTY; + /* + * Future Zhaoxin Root Ports and Switch Downstream Ports will + * implement ACS capability in accordance with the PCIe Spec. + */ switch (dev->device) { case 0x0710 ... 0x071e: case 0x0721: - case 0x0723 ... 0x0732: + case 0x0723 ... 0x0752: return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); }
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ea476252280a..f4546590d9e3 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4706,10 +4706,14 @@ static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) return -ENOTTY; + /* + * Future Zhaoxin Root Ports and Switch Downstream Ports will implement ACS + * capability in accordance with the PCIe Spec. + */ switch (dev->device) { case 0x0710 ... 0x071e: case 0x0721: - case 0x0723 ... 0x0732: + case 0x0723 ... 0x0752: return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); }