@@ -104,6 +104,7 @@ struct imx6_pcie_drvdata {
const u32 ltssm_mask;
const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
+ const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx6_pcie *pcie);
};
@@ -1101,7 +1102,10 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
static const struct pci_epc_features*
imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
- return &imx8m_pcie_epc_features;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+
+ return imx6_pcie->drvdata->epc_features;
}
static const struct dw_pcie_ep_ops pcie_ep_ops = {
@@ -1588,6 +1592,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.mode_off[1] = IOMUXC_GPR12,
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
+ .epc_features = &imx8m_pcie_epc_features,
.init_phy = imx8mq_pcie_init_phy,
},
[IMX8MM_EP] = {
@@ -1598,6 +1603,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.gpr = "fsl,imx8mm-iomuxc-gpr",
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .epc_features = &imx8m_pcie_epc_features,
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
@@ -1606,6 +1612,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.gpr = "fsl,imx8mp-iomuxc-gpr",
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .epc_features = &imx8m_pcie_epc_features,
},
};
The i.MX EP exhibits variations in epc_features among different EP configurations. This introduces the addition of epc_features in imx6_pcie_drvdata to accommodate these differences. It's important to note that there are no functional changes in this commit; instead, it lays the groundwork for supporting i.MX95 EP functions. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- Notes: Change from v1 to v3 - new patch at v3 drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)