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b=Cf687BAhoSIexO2hZaSJVHmtaS6/acaq3q3VCf4rfz2AhZNIPlLJUeNxxN1wAA0g3Od/eJSND4i21WlSJ/Mm+dSyoaYOEDU8xeSyYtRYSgqpwMzKkgnnCqJYYeVmD/GYTSf84LLgU8c8lGv5814GDfgvNQxEusav8X5D+vHGG4A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by AS5PR04MB10020.eurprd04.prod.outlook.com (2603:10a6:20b:682::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.26; Sun, 24 Dec 2023 18:33:17 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.026; Sun, 24 Dec 2023 18:33:17 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v6 03/16] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Sun, 24 Dec 2023 13:32:29 -0500 Message-Id: <20231224183242.1675372-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231224183242.1675372-1-Frank.Li@nxp.com> References: <20231224183242.1675372-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0169.namprd03.prod.outlook.com (2603:10b6:a03:338::24) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|AS5PR04MB10020:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c3fa283-5594-45e0-475f-08dc04aecba6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +62e2MobEIdJ2BJp8DppPTmzdsnjhx4PGi+Ic5ouTr8ozRilx21tBPZtPR4QoeYojLrrnyG0c1amkQ2egkuA8TdhfahdNHT+XvK6g/Km2NdEIm6nrHUUsxt5qA2oCzT3Ts8rnoW5jFmM6gQmiMYoE96+tbGmvmdhDU0BKnsK0M415ZAF8qHCX13Xv55HPcrGz6jwCVNDG2q6IeGu69hGy/XaO8AWGGSbqahWRUYLHGHMvZF+cv7bDxKrIH3iJ2bsPILAKbeiOCF1r7edYg7wdCbyS9zf1ZeQO7vZp4sGgTcXKnVAdsh3ANd5DJZL2QAnyaPr7mvkWnqY2mTtM4/uJdDruuKjKcGMgJ/bzpCfGFtgyuU2EKBYbWcg2c1FZ1FYrdI5CrNqd8nZLZf0VrEPItxDPUFNZYx8zbkVfbWbb5oESf7qRlu9mF3dCnjLdL0EAKAZOqyCf5NzqrUHsDfAwIIzA0ca1m2XuAEnH5lui4xZdAnlSJaj+uvByKO6/OGeeUfdopsGbjLVMmuA+7zvheQV2R67HUSELF6k8goyRkJb0+btOiJYvJ7n/LLaFbxaPBfMYNxSSqc4XaULzpSf/EKOz3WTqszZjJc/CDDlGiNxdKnvbtpE6jlifIIhnrFmZjSM2LUkfQ3e25dgiKvyd9csn2PAjP2tDAkRt+0AOcc0SuFCz05QjozF6OeXZfk/9/3DWbFRkeXHjfM7eLKb25N5mlEUDOOL9VOUEmexRkn+8MaRXQwK0brqLq8KmL5n0ov1QTmaj8uREN+ftBOmtodkJmldBrJu8Fm1c1DkG0euRzqwJwYLdlFa7Bz/RCsDNE2EdbCNIHyn7T+5cFaABDIgk4Aq7U7/vYPQpw65njFby5may2XwCMDUtkCQmeOid+OYJh9cMoiZf+/sQXLL2MdEEi5sX6b+NiecF6E2mCEyuWD48KGBhH/7/bL0nnNBLILeU7h0ELC97J5K6tjF90TnZFY6M5i+saup7hCShiepSwJ/G5wBTMRtEqQ549nBhz74zzOmOO23Gnjr8HcC1Y0ks6DWt0Ht1b0/dkBDAo+et2ggbzwsIPyb0dc5KXX7Yo8BS5ckwq9MVB2pMUbVAnXICYHVY78oVaNLRZiQdidS3Ncygf+A6m1sCBarQbbZprynKyd0A1oYS1zh+6EOxlB2SjwkjZ6fABSUOQjAMsYD2g1+ifFZf4d/ZQ5dsz5F7pfv9ombccmyPJNyT49ykM4mcH9rSmrzcbCCVxlEibI5btN8AvrDt4jatKQLiEOHqZzYRjyNqf9DAuo8TuQowtM3v4O1ecbIfVtwXuwmtsZM7X1659/ZqOkwkIxcL1TDT2+q8fIuikDDVUmXKvQdoImlNMT5k6zlgBCzAaUUvWWLnoMNB9CkV66kYNrC2IA/Kzd8xeWN0quurvv9iXT7uIQfBC6BnONGxUVJTumJP+uG2R+8VUmx3BYLgmqJlgZ5RvSsVgvGBB3gfbnBoouuG1YlCQ429GqC0i2lkHxmtE1uvot4rTYXFTIYTHvpIdlMZ6OToSHqcheGx+navOWwnA5uDaasjmI/1HQiyjAK3EM= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8c3fa283-5594-45e0-475f-08dc04aecba6 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2023 18:33:17.0140 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ozbaC3sEt90Tuv9vKgDZlfDzzzqTWDj63L2SJC8W4hgQHzDGEVothUwGdN963i9id1XngaVsrhkbsP7hUED5FA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB10020 Refactors the reset handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_*_RESET bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Signed-off-by: Frank Li --- Notes: Change from v4 to v5: - Add Mani's Reviewed-by tag - Fixed MQ_EP's flags Chagne from v3 to v4: - none Change from v2 to v3: - add Philipp's Reviewed-by tag Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. drivers/pci/controller/dwc/pci-imx6.c | 108 ++++++++++---------------- 1 file changed, 41 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 4d620249f3d52..294f61a9c6fd9 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,6 +61,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) #define IMX6_PCIE_FLAG_HAS_PHY BIT(3) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -661,18 +663,10 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + reset_control_assert(imx6_pcie->pciephy_reset); + reset_control_assert(imx6_pcie->apps_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); - break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -693,6 +687,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -706,14 +702,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; case IMX7D: - reset_control_deassert(imx6_pcie->pciephy_reset); - /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -745,11 +737,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -796,16 +784,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -819,16 +802,11 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1287,36 +1265,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1438,31 +1404,39 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, }, [IMX8MQ] = { .variant = IMX8MQ, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},