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b=fgO6asKJ67uEFxYYXUVxzmsou9sp7JmdpAYsLl2vhOWiOgx0k/AVDzVtXdq3ar1QCI9aEq5h4xa1gY+7lfeucosH4M8VM65shLEEWIPKo3jRngJ3AFMZiCawSA800uTg3A1UpE/gRP8vAbscjRPNd42vIOw++GpTiavCDP5tk6A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:05 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:05 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 03/16] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Wed, 27 Dec 2023 13:27:14 -0500 Message-Id: <20231227182727.1747435-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: b6e641f5-cfe8-485b-120b-08dc07099146 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jqoyXje/A5JaC0aqxXtpNBaxc/EpE23a8eyMnDeHQTAWIkh/X0BmO0F1VIcjcGpHXcs8xYjcF6OeHyqoyQ/HpHOax5rvogLgx9IAWETID/8HQGlsI/mkq5M9b6dE+duKF+N3ADyB/tBrpFdj8S72c8BBi7Wg65+k5Xlv8sxZkZZzi1cOC8v2LVtY5Hi+SCzO6Kt/NQcaAzjWzmCQX8GsuY0cB8txvzBKJFQm45E52osAv5puFBjEo1E8D7kvrjALtWPTxVtqvYEBdPS8AEI5BKtsCNIxQOSLZfzhmAm5pmMIpIlY7auAlaNbPUFoAzpqPVmTktwD1BP2FUiyp+M2K+mpsnTEBrVU3Suck1V72P6xlyx1SFj5zGDoMwqzKkdDvyQACNJJ3bfDKvnTRlv2dl0fK1MeY0m6ZO51R9E3woP7GsJLXEPICSqGu6DJkO4Pn+ICtllYgHZa/ThEqgaRdDnU2b7YQMB/UhCTFz2C+p1laEs6xzo+ia7WoCT/Kv8sqb/3bKmjORCkeZiXMx7WY/piWz+r/7ZG1kuSro5KcVHVZjP/L6E9cnXBtV9ypyh2/D06RaRp0uwGxl5YmyPj9e/SskCaL1Fw0xK8NhBJE7finAh44MYQQA0+DkiiVmbXX0p2MFi7l4mg3KZ66laD4WzOlodfZZ5dfIsOYIhbFz9eY4bONX4TYHfkiQiEP3bdq0V/kyjCs0lfFFb/Oaxjcmh6ybIcM3EThcFj+VSFTOa/RIeYtcjDAR7JAr6byKjSWoqzONk23U5Om7Og0L0p77W0THErByAmX6WWhLdclHYduLS5/EeFUZgxisYck2D6T9itDZxS22nmosHBG8Bj40F7Xt6XMRdBApUSshildCFoUizGAsoq2xO4dZVSt0ta9qiSP2coC/X4DjSaebru7PDYw+OAzsyui0DSrQnjtS/XVt1Ay4XyesQRdQastFC6XHPRsHnBsq6XFmxM0pPOpTiTQZhAbB7D547xnGn3F2/rRNCODA04YlETY3/Xq6RwouWyZHuOIcPGcKkHwDtBigEVqM96M9tceKG3bwpQSLb33stmFs33bw9/3wUpQhWjt1gSFoUVosof0opbkZJm/gi08a5YcQAHHSvbzY0pouJ8aTyRpg+3p/1NWHV+LKlXlGALvobFcLeYY+YS8bvj2SSxJq3QblVx0nmf9FJy/lqNSkj1t+G+53GEaxPh2t4n3GslHZ3LPc4ekfEw0Uy2TM9ZbLmHWeiF4aao2+66pMPi5YU4geyXtscIzyg9P7QYjvGFQyL4whUiGnfSy04Z/+H9xy4fBnVDp0NqSWSAHm/TCe6C/tKa1Xfw2oDj/GiEpsYZSd6QY4NXQIgiPjBejZ4h4TVvpoJBjjOOJ8QZbZCFzH1X2gttKSEhYiVVQIjJiXBTVnkuAbyEQELKB+pLUcjKhhRYvi7v+QpY4G0JSJtdnPCCmy8cJEB7wlZYGJR+0ndOvnDnAoXp/N7+27xKqHfafOq2R5Esx3ANtNXlT9FZmBlYGMRxoznl6TNPmOk1gVnAw1rULzX7f+ePt37f5ZdNbZShME6nxn3OLBPe5jg= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6e641f5-cfe8-485b-120b-08dc07099146 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Dec 2023 18:28:05.5804 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oMypvFw7fA8q4e15XNrcUVIa5D+NSh67h7MnhkYmfavPbS33IGRR2HXvsIMtJwBbPQ7ogU88gDKHchPPwtBmUQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9050 Refactors the reset handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_*_RESET bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Signed-off-by: Frank Li --- Notes: Change from v4 to v5: - Add Mani's Reviewed-by tag - Fixed MQ_EP's flags Chagne from v3 to v4: - none Change from v2 to v3: - add Philipp's Reviewed-by tag Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. drivers/pci/controller/dwc/pci-imx6.c | 108 ++++++++++---------------- 1 file changed, 41 insertions(+), 67 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 4d620249f3d52..294f61a9c6fd9 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,6 +61,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) #define IMX6_PCIE_FLAG_HAS_PHY BIT(3) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -661,18 +663,10 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + reset_control_assert(imx6_pcie->pciephy_reset); + reset_control_assert(imx6_pcie->apps_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); - break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -693,6 +687,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -706,14 +702,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; case IMX7D: - reset_control_deassert(imx6_pcie->pciephy_reset); - /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -745,11 +737,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -796,16 +784,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -819,16 +802,11 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1287,36 +1265,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1438,31 +1404,39 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy"}, }, [IMX8MQ] = { .variant = IMX8MQ, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},