From patchwork Thu Dec 28 00:16:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ethan Zhao X-Patchwork-Id: 13505527 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E48A637; Thu, 28 Dec 2023 00:16:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nIit7FxY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703722615; x=1735258615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E0MhZ0JF1VXMX0GUVKCEwMF1hc/wfxdlOt1kMXlN/dc=; b=nIit7FxYGJIPxdQ9P0K6QgJXfKldNZTsHRG1+pK/f+a/DVXqjBxizb7j u/nkyV/KVhT/UL1MLUrtK+gQ7tQFZj/4afyrjEYnYlXgjyzEISBvViMfy Q5zLTXQeb2lXlvE0UhL2RXdymv6IxM+kLewPNASGvRajXZHXjWOmB4ljr 7DA4s4Lk12o7Ji/bTloWk2NPVWv/XSGPN0YBONHTbDWdktWPCEAQT6U0b JJDIf4mXmo7dg9+HMQ+vdg/kfETgzI4WJ9zUeoGiS2lC4wLkjw2G5dnZ2 N1FXe/0JRHdykyjmQLx7g7K+QDajTwlo9ZkDA3KDcCslwU7DrF2NevVLt w==; X-IronPort-AV: E=McAfee;i="6600,9927,10936"; a="3800448" X-IronPort-AV: E=Sophos;i="6.04,310,1695711600"; d="scan'208";a="3800448" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2023 16:16:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10936"; a="848812665" X-IronPort-AV: E=Sophos;i="6.04,310,1695711600"; d="scan'208";a="848812665" Received: from ply01-vm-store.bj.intel.com ([10.238.153.201]) by fmsmga004.fm.intel.com with ESMTP; 27 Dec 2023 16:16:51 -0800 From: Ethan Zhao To: bhelgaas@google.com, baolu.lu@linux.intel.com, dwmw2@infradead.org, will@kernel.org, robin.murphy@arm.com, lukas@wunner.de Cc: linux-pci@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC PATCH v9 1/5] iommu/vt-d: add flush_target_dev member to struct intel_iommu and pass device info to all ATS Invalidation functions Date: Wed, 27 Dec 2023 19:16:42 -0500 Message-Id: <20231228001646.587653-2-haifeng.zhao@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231228001646.587653-1-haifeng.zhao@linux.intel.com> References: <20231228001646.587653-1-haifeng.zhao@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As iommu is a pointer member of device_domain_info, so can't play trick like container_of() to get the info and device instance for qi_submit_sync() low level function to check device status, add a flush_target_dev member to struct inte_iommu and pass dev info to all device-TLB invalidation (a.k.a ATS Invalidation) functions. Signed-off-by: Ethan Zhao --- drivers/iommu/intel/iommu.c | 1 + drivers/iommu/intel/iommu.h | 2 ++ drivers/iommu/intel/pasid.c | 1 + drivers/iommu/intel/svm.c | 1 + 4 files changed, 5 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 897159dba47d..c3724f1d86dc 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1461,6 +1461,7 @@ static void __iommu_flush_dev_iotlb(struct device_domain_info *info, sid = info->bus << 8 | info->devfn; qdep = info->ats_qdep; + info->iommu->flush_target_dev = info->dev; qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, qdep, addr, mask); quirk_extra_dev_tlb_flush(info, addr, mask, IOMMU_NO_PASID, qdep); diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index ce030c5b5772..e892c5c7560a 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -731,6 +731,8 @@ struct intel_iommu { void *perf_statistic; struct iommu_pmu *pmu; + + struct device *flush_target_dev; /* the target device TLB to be invalidated. */ }; /* PCI domain-device relationship */ diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 74e8e4c17e81..1c87fb1b1039 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -485,6 +485,7 @@ devtlb_invalidation_with_pasid(struct intel_iommu *iommu, qdep = info->ats_qdep; pfsid = info->pfsid; + info->iommu->flush_target_dev = info->dev; /* * When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID), * devTLB flush w/o PASID should be used. For non-zero PASID under diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index ac12f76c1212..d42a99801cdf 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -181,6 +181,7 @@ static void __flush_svm_range_dev(struct intel_svm *svm, qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, address, pages, ih); if (info->ats_enabled) { + info->iommu->flush_target_dev = info->dev; qi_flush_dev_iotlb_pasid(sdev->iommu, sdev->sid, info->pfsid, svm->pasid, sdev->qdep, address, order_base_2(pages));