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Tue, 9 Jan 2024 19:07:35 -0800 From: Vidya Sagar To: , , , , , , , CC: , , , , , , , , , Subject: [PATCH V2 1/2] dt-bindings: Add PCIe "preserve-boot-config" property Date: Wed, 10 Jan 2024 08:37:24 +0530 Message-ID: <20240110030725.710547-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240110030725.710547-1-vidyas@nvidia.com> References: <20240110030725.710547-1-vidyas@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|BL3PR12MB6642:EE_ X-MS-Office365-Filtering-Correlation-Id: 8eb49b61-23b1-40eb-6b2f-08dc11895825 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9RbD36VCUWwyoyO/scX0Qa4wUsBgfGYPTpc4RSRmfZ99Mi1FGmKZ74o3PazT9x2ej9Uv3NZRdg73m6HmSOOHnrR5znuLvTUGfkZf14G9YLOfq71iebqD3Ouai4Lx7G9VovmTmFal9PCQwQzhaIgNvZG5+EJQa6Zn2hBOC8Xl/YqXCm5Fb4LMVSuQpC/ucFKV6UV6rEqdqzWkmpzShVYhL8HllCcHr9rb5AA4VhAUoxSn4200BoxQQL+HMf30q7GPAyHltTyqeG5x8wJR38zY/AJkuLJHpqD5egCCJt8hq0UGft84RW2nDlAAp5FM0EDPGl8Q46jt7e90Ht/FqF88tgupnPQCBuueZQQ1gZqInalis4n9XeDsFrfwDVvNwJQHgnsxwOiUsGHnVpOMNOGjlhjxHoKszYDjCKRk+nOlIp4Wx0V2B87lNfGmlsZS3JpKS3LbcdF3DgV1x9e5LS0r8LSoH8Nv6YFsDfByHNXs8gF63nOlgd6A7/nMIUl7ruYd8tkfMt5mQ3Wzb4veFqTpqeYctKFnmseQrESq4rwRtl52rclF4FEoHh68eaemGbFqW35xMBsWIqLf02pDMBkM4n9E8DfA9xI+LPynR+St9JBm69taHqKdeg7H/q8YmYeVacDqLSJfsTtXR8kzBz/Pl8vqNn3HAquuY9MGuDm1WdSJh/3SZUSZgp8XkdYwJKn51uI+RlGrVI/BNVC5Rd9UbJzIuTSnzwDYbjxJPvSiza+0Ws3g0fh9omxqaaCb46X6 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(136003)(346002)(396003)(230922051799003)(1800799012)(451199024)(82310400011)(186009)(64100799003)(36840700001)(40470700004)(46966006)(2906002)(7416002)(5660300002)(41300700001)(478600001)(7636003)(82740400003)(2616005)(426003)(1076003)(26005)(40480700001)(336012)(40460700003)(356005)(6666004)(7696005)(47076005)(36860700001)(8676002)(8936002)(4326008)(36756003)(110136005)(70586007)(54906003)(86362001)(70206006)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2024 03:07:56.5556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8eb49b61-23b1-40eb-6b2f-08dc11895825 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6642 The existing "linux,pci-probe-only" property applies at a system level and it is not possible to selectively convey individual host bridge's requirement w.r.t preserving the boot configuration done by the platform firmware to the kernel. "preserve-boot-config" addresses that concern and can be used to preserve the boot configuration for host bridges selectivey. Signed-off-by: Vidya Sagar --- V2: * None Documentation/devicetree/bindings/pci/pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..0a5ff998cbe8 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -32,6 +32,10 @@ driver implementation may support the following properties: root port to downstream device and host bridge drivers can do programming which depends on CLKREQ signal existence. For example, programming root port not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. +- preserve-boot-config: + If present this property specifies that this host bridge is already + configured by the platform firmware and the OS doesn't need to reconfigure + it again. PCI-PCI Bridge properties -------------------------