| Message ID | 20240228190321.580846-2-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: pci: layerscape-pci: Convert to yaml format | expand |
On Wed, 28 Feb 2024 14:03:17 -0500, Frank Li wrote: > Split layerscape-pci.txt into two yaml files: fsl,layerscape-pcie-ep.yaml > and fsl,layerscape-pcie.yaml. > yaml files contain the same content as the original txt file. > > The subsequent commit will fix DTB_CHECK failure. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 89 +++++++++++++ > .../bindings/pci/fsl,layerscape-pcie.yaml | 123 ++++++++++++++++++ > .../bindings/pci/layerscape-pci.txt | 79 ----------- > 3 files changed, 212 insertions(+), 79 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'msi-parent', 'ranges', 'reg-names' were unexpected) from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: 'fsl,pcie-scfg' is a required property from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: 'dma-coherence' is a required property from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240228190321.580846-2-Frank.Li@nxp.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Wed, Feb 28, 2024 at 03:03:31PM -0600, Rob Herring wrote: > > On Wed, 28 Feb 2024 14:03:17 -0500, Frank Li wrote: > > Split layerscape-pci.txt into two yaml files: fsl,layerscape-pcie-ep.yaml > > and fsl,layerscape-pcie.yaml. > > yaml files contain the same content as the original txt file. > > > > The subsequent commit will fix DTB_CHECK failure. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 89 +++++++++++++ > > .../bindings/pci/fsl,layerscape-pcie.yaml | 123 ++++++++++++++++++ > > .../bindings/pci/layerscape-pci.txt | 79 ----------- > > 3 files changed, 212 insertions(+), 79 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): Please omit these errors. Bjorn require create a identical version as old txt file. Origial txt will cause DTB_CHECK error. The problem will be fixed at next patches. > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'msi-parent', 'ranges', 'reg-names' were unexpected) > from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: 'fsl,pcie-scfg' is a required property > from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: 'dma-coherence' is a required property > from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240228190321.580846-2-Frank.Li@nxp.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. >
On Thu, Feb 29, 2024 at 12:43:29PM -0500, Frank Li wrote: > On Wed, Feb 28, 2024 at 03:03:31PM -0600, Rob Herring wrote: > > > > On Wed, 28 Feb 2024 14:03:17 -0500, Frank Li wrote: > > > Split layerscape-pci.txt into two yaml files: fsl,layerscape-pcie-ep.yaml > > > and fsl,layerscape-pcie.yaml. > > > yaml files contain the same content as the original txt file. > > > > > > The subsequent commit will fix DTB_CHECK failure. > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > > --- > > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 89 +++++++++++++ > > > .../bindings/pci/fsl,layerscape-pcie.yaml | 123 ++++++++++++++++++ > > > .../bindings/pci/layerscape-pci.txt | 79 ----------- > > > 3 files changed, 212 insertions(+), 79 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > > > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > Please omit these errors. Bjorn require create a identical version as > old txt file. > > Origial txt will cause DTB_CHECK error. The problem will be fixed at next > patches. One of these is a real error - caused by a typo. "dma-coherence" should be "dma-coherent". > > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'msi-parent', 'ranges', 'reg-names' were unexpected) > > from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: 'fsl,pcie-scfg' is a required property > > from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.example.dtb: pcie@3400000: 'dma-coherence' is a required property > > from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# > > > > doc reference errors (make refcheckdocs): > > > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240228190321.580846-2-Frank.Li@nxp.com > > > > The base for the series is generally the latest rc1. A different dependency > > should be noted in *this* patch. > > > > If you already ran 'make dt_binding_check' and didn't see the above > > error(s), then make sure 'yamllint' is installed and dt-schema is up to > > date: > > > > pip3 install dtschema --upgrade > > > > Please check and re-submit after running the above command yourself. Note > > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > > your schema. However, it must be unset to test all examples with your schema. > >
On Thu, Feb 29, 2024 at 12:43:29PM -0500, Frank Li wrote: > On Wed, Feb 28, 2024 at 03:03:31PM -0600, Rob Herring wrote: > > > > On Wed, 28 Feb 2024 14:03:17 -0500, Frank Li wrote: > > > Split layerscape-pci.txt into two yaml files: fsl,layerscape-pcie-ep.yaml > > > and fsl,layerscape-pcie.yaml. > > > yaml files contain the same content as the original txt file. > > > > > > The subsequent commit will fix DTB_CHECK failure. > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > > --- > > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 89 +++++++++++++ > > > .../bindings/pci/fsl,layerscape-pcie.yaml | 123 ++++++++++++++++++ > > > .../bindings/pci/layerscape-pci.txt | 79 ----------- > > > 3 files changed, 212 insertions(+), 79 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml > > > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > Please omit these errors. Bjorn require create a identical version as > old txt file. > > Origial txt will cause DTB_CHECK error. The problem will be fixed at next > patches. Nope. We can't have warnings. Please fix them in the conversion. Call out the changes in the commit message. Rob
diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml new file mode 100644 index 0000000000000..0af70a4bc5d91 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + + This controller derives its clocks from the Reset Configuration Word (RCW) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'version' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller version + information. + +properties: + compatible: + items: + - enum: + - fsl,ls1028a-pcie-ep + - fsl,ls2046a-pcie-ep + - fsl,ls2088a-pcie-ep + - fsl,ls1046a-pcie-ep + - fsl,ls1043a-pcie-ep + - fsl,ls1012a-pcie-ep + - fsl,lx2160ar2-pcie-ep + - const: fsl,ls-pcie-ep + + reg: + description: base addresses and lengths of the PCIe controller register blocks. + + interrupts: + description: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + + interrupt-names: + minItems: 1 + maxItems: 3 + description: It could include the following entries. + items: + oneOf: + - description: + Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used. + const: aer + - description: + Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used. + const: pme + - description: + Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). + const: intr + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Must include two entries. + The first entry must be a link to the SCFG device node + The second entry is the physical PCIe controller index starting from '0'. + This is used to get SCFG PEXN registers + + dma-coherent: + description: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, specify + this property. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-names + - fsl,pcie-scfg + - dma-coherence + diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml new file mode 100644 index 0000000000000..c37578fde8bb1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + + This controller derives its clocks from the Reset Configuration Word (RCW) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'version' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller version + information. + +properties: + compatible: + enum: + - fsl,ls1021a-pcie + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + - fsl,ls1088a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + - fsl,ls1028a-pcie + - fsl,lx2160a-pcie + + reg: + description: base addresses and lengths of the PCIe controller register blocks. + + interrupts: + description: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + + interrupt-names: + minItems: 1 + maxItems: 3 + description: It could include the following entries. + items: + oneOf: + - description: + Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used. + const: aer + - description: + Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used. + const: pme + - description: + Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). + const: intr + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Must include two entries. + The first entry must be a link to the SCFG device node + The second entry is the physical PCIe controller index starting from '0'. + This is used to get SCFG PEXN registers + + dma-coherent: + description: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, specify + this property. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-names + - fsl,pcie-scfg + - dma-coherence + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt deleted file mode 100644 index ee8a4791a78b4..0000000000000 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ /dev/null @@ -1,79 +0,0 @@ -Freescale Layerscape PCIe controller - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in snps,dw-pcie.yaml. - -This controller derives its clocks from the Reset Configuration Word (RCW) -which is used to describe the PLL settings at the time of chip-reset. - -Also as per the available Reference Manuals, there is no specific 'version' -register available in the Freescale PCIe controller register set, -which can allow determining the underlying DesignWare PCIe controller version -information. - -Required properties: -- compatible: should contain the platform identifier such as: - RC mode: - "fsl,ls1021a-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" - "fsl,ls2088a-pcie" - "fsl,ls1088a-pcie" - "fsl,ls1046a-pcie" - "fsl,ls1043a-pcie" - "fsl,ls1012a-pcie" - "fsl,ls1028a-pcie" - EP mode: - "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" -- reg: base addresses and lengths of the PCIe controller register blocks. -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: It could include the following entries: - "aer": Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used - "pme": Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used - "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). -- fsl,pcie-scfg: Must include two entries. - The first entry must be a link to the SCFG device node - The second entry is the physical PCIe controller index starting from '0'. - This is used to get SCFG PEXN registers -- dma-coherent: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly. - -Optional properties: -- big-endian: If the PEX_LUT and PF register block is in big-endian, specify - this property. - -Example: - - pcie@3400000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - };
Split layerscape-pci.txt into two yaml files: fsl,layerscape-pcie-ep.yaml and fsl,layerscape-pcie.yaml. yaml files contain the same content as the original txt file. The subsequent commit will fix DTB_CHECK failure. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 89 +++++++++++++ .../bindings/pci/fsl,layerscape-pcie.yaml | 123 ++++++++++++++++++ .../bindings/pci/layerscape-pci.txt | 79 ----------- 3 files changed, 212 insertions(+), 79 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt