From patchwork Wed Mar 20 11:31:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13597801 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A080B3D961 for ; Wed, 20 Mar 2024 11:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710934352; cv=none; b=apHe5e4nKpGCkRaV+RbwuHO7vzW9Qg7AuYFL0IXr6PKLF3sD3OCYPED88Ln4Wc1i/BARm7sx4vzVgEt653pdbqJEIK5PqYKB2CyA2sguvseQp4xfaKIItJJNGL/hXfHTxDquJtSKdBpc0QpeJQxTszJHA5d7j7HO33dcYpMtiJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710934352; c=relaxed/simple; bh=q66K0XDfqa4FH1mzvBlDGOW/HIb2nk503TpvzVrO3uw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ETO6m/APr4BkxBRcGQR8ZNTv23c30J894oUREqRfQuSColonZP1B119Qy+gnQ6Q1cWBS9YRfsDMyjL52buZaHvDCKwkCzRIpPjetr+/RIKaBBdC1MlFjtJd2qOwU3TQZVYVHvtE54uufKxncbBOJL+HLIv/fiuaFVmqYmXLIXbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b0z853G/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b0z853G/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A65BC433B1; Wed, 20 Mar 2024 11:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1710934352; bh=q66K0XDfqa4FH1mzvBlDGOW/HIb2nk503TpvzVrO3uw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b0z853G/KCqIKbAzHMyET5yPiC7NK9lhx6S1JnpJ9Bn8BYyNrNZtk2RWP/rw2QKGZ 4/wlPBkWWEsHZ7UVFUbIYaOCWcJHakfF12kS1JMAMdzAHEXAguURm59a7Rkt5DHvzj SbkbieyE2zIIXHVDLLvQR0uSCJ1ybo2901O1svpFTIiq6Wm2IMfzPEVdUq3F3dm6Ae x8dYsbKKphtdT8cCnOb2jF0NRVezO5BlHl5zviXSG+n2hVOvQlwMorxgPxE8B1U9e1 B5lyaIClz7Ot/n1M1vf8TOY0IXZRtApjsRYNtfkAeMBkcRXts0NNLIbPUCQPTQsj7W h0mQZgU+k+SxA== From: Niklas Cassel To: Manivannan Sadhasivam , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Shradha Todi , Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 7/7] PCI: rockchip-ep: Set a 64-bit BAR if requested Date: Wed, 20 Mar 2024 12:31:54 +0100 Message-ID: <20240320113157.322695-8-cassel@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240320113157.322695-1-cassel@kernel.org> References: <20240320113157.322695-1-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not set") it has been impossible to get the .set_bar() callback with a BAR size > 2 GB (yes, 2GB!), if the BAR was also not requested to be configured as a 64-bit BAR. It is however possible that an EPF driver configures a BAR as 64-bit, even if the requested size is < 4 GB. Respect the requested BAR configuration, just like how it is already repected with regards to the prefetchable bit. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/pcie-rockchip-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index c9046e97a1d2..57472cf48997 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS; } else { bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); - bool is_64bits = sz > SZ_2G; + bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64); if (is_64bits && (bar & 1)) return -EINVAL;