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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?9Bws7Z0d+5SK8UhgyQy5Hc/20teP?= =?utf-8?q?JhPcZP/R1TYx9eXAtduHkun3WAA+vYaWA46PiOFSMflLCTvjssNd2rBZuJ9n9ujwA?= =?utf-8?q?r+jWjgnSgdSupDKaRUp2hnet1vsBSII82LeZvv53AYDrCr8g0bpS5pqpA8fzQEDit?= =?utf-8?q?dn9x20KT7rQZel+DHCxm3bNY9+d1lt58JqpMPFMSxXwLKdG7689Y6VVfPgZSX6fKE?= =?utf-8?q?5AuEyFChgB1up6FmIUDGstrKsYYOR4YizNswFamcc0BdprSaLNhFcuv/AnVPBxr5L?= =?utf-8?q?TJ2XwqssQt7L2P7WLF8PfWlFzWwTXFBw/lhgCMZ+bcqSHhCWxwlxtYP2swig7Zy87?= =?utf-8?q?fp223oOQ2Ux59euiji15vBfemJABvfQE1BkcyV1PO0VUbns5PWdMSrS3QwOHfxlwQ?= =?utf-8?q?LeRbGDG3G2msyB/wBUyxc+EAbdAwAlrMbxMg9nRkj+W131VdwY9uFBqtFGDj6wSMK?= =?utf-8?q?6LB4PxAkBe5GrmnIJ0xzESDjI2dcoGVujn8ABuXkx0BgGLxbu/tt0x/Q85DY36GYP?= =?utf-8?q?zgxgd2GNzZyZEZ24QilHFjSgT4eGu//O4JSn5dtUugNB6jG5jVJI4L/qLMpbR56y/?= =?utf-8?q?qTWb0LuaUIRpfl0a1hLsvUsBnBa5JCiUJT3Fo2yWs4RNI0X1nN43iSIwd9EIITWtJ?= =?utf-8?q?WYhZYaHc3JxiDMJpt+0LWkFJysMle2NAqreT8gMOF46EJEoAAqXpa2BZEVUwnOy1w?= =?utf-8?q?Q1srfkeIlCXe5QqHtervCNi6Tm22XTpd5orD/rguFSt3kEjWFJa92tzXu9UYi4/qk?= =?utf-8?q?lafXGIVaedlvl/WI+hWlaABl6lu+XwlrFJKwnYCLIVefNftiuekQ2KQNezndFKRlF?= =?utf-8?q?/Y71ch73m20hHaISMFwiqDQwjSoH+1jZJ3DVtE9J32//MNTY7BWUi18lpOeqMI4B4?= =?utf-8?q?q6w0JizxarCTDUkEYtiMsc9vTP8IpxJXSvIRmTc7tIE3lS5iwmOodd5ZY/Fghzjuv?= =?utf-8?q?KrCHKHkUK6OHTOrsCcC4AI5mtB+b0d8VC3XrdV+gbx99vuAciewW03H5mQiAb7yMu?= =?utf-8?q?na33UynM0gp1u9ghi5Wq/f39/CsUawpbUqoVG8NmbIr7lQSihTJp3t95wOVDyFqR1?= =?utf-8?q?R0D7GxibsYBmSwTdYsAZ4PBKvesPvVD55L7hAXvkWHs8/fKvgJ0mSN1FPLdHQ7PRL?= =?utf-8?q?Q6YjDfs4Ft+CYN6TVSaGgaQ8EeMXiFZ0xgPdexGxWl3ottQiYs5Kz8UOGeycSTpEG?= =?utf-8?q?67Yo/DnIzCAXPzXWVbGNb91oSN96XwGDi+/baFqlzx+yykcmvmSGQsojCF78lYpRl?= =?utf-8?q?R24RPeQkLN4fWjI29AhQAkkWz18CMHsR1Qny9NgI2S3YtrximmAxsGvrdbZ6F5SVk?= =?utf-8?q?6onzg/7XnTqJk0bSs1xj6uK7visIyJ8kkmLXJdZeLqS5IMoKiDFSrF5C76TmPVGg6?= =?utf-8?q?1+vpjc7Dl3HywwzflUAqrQwYHQhJ44d6qEpiOSF30tiUf5ax6I1FkCSkj2xDFQtBh?= =?utf-8?q?+OXW4PjY87psXdIgiytJPGiFTgGGO9p/Od9TS55YEkQlJb7Dwb/uAkPQ=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f937455f-d1f3-4093-05bf-08dc53220354 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2024 14:34:33.0867 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KLS89qlMGFhVBjGXigtv15AJ7oaxm9xFEkFvUXCAn12ffiydEt9HqqwwLGMdU8iRMw6Gs5SJixQwbK6aQbM94Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8926 Instead of using the switch case statement to assert/dassert the core reset handled by this driver itself, let's introduce a new callback core_reset() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-imx.c | 131 ++++++++++++++++++---------------- 1 file changed, 68 insertions(+), 63 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c index 77dae5c3f7057..af0f960f28757 100644 --- a/drivers/pci/controller/dwc/pcie-imx.c +++ b/drivers/pci/controller/dwc/pcie-imx.c @@ -104,6 +104,7 @@ struct imx_pcie_drvdata { const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); + int (*core_reset)(struct imx_pcie *pcie, bool assert); }; struct imx_pcie { @@ -671,35 +672,72 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + assert ? IMX6SX_GPR12_PCIE_TEST_POWERDOWN : 0); + /* Force PCIe PHY reset */ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); + return 0; +} + +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); + if (!assert) + usleep_range(200, 500); + + return 0; +} + +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, + assert ? IMX6Q_GPR1_PCIE_TEST_PD : 0); + + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, + assert ? 0 : IMX6Q_GPR1_PCIE_REF_CLK_EN); + + return 0; +} + +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + + if (assert) + return 0; + + /* + * Workaround for ERR010728, failure of PCI-e PLL VCO to oscillate, especially when cold. + * This turns off "Duty-cycle Corrector" and other mysterious undocumented things. + */ + + if (likely(imx_pcie->phy_base)) { + /* De-assert DCC_FB_EN */ + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); + /* Assert RX_EQS and RX_EQS_SEL */ + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); + /* Assert ATT_MODE */ + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); + } else { + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); + } + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); + return 0; +} + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { reset_control_assert(imx_pcie->pciephy_reset); reset_control_assert(imx_pcie->apps_reset); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - /* Force PCIe PHY reset */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, - IMX6SX_GPR5_PCIE_BTNRST_RESET); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, - IMX6Q_GPR1_PCIE_SW_RST); - break; - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, true); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) @@ -709,47 +747,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx_pcie->pci; - struct device *dev = pci->dev; - reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx_pcie->drvdata->variant) { - case IMX7D: - /* Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. - */ - if (likely(imx_pcie->phy_base)) { - /* De-assert DCC_FB_EN */ - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx_pcie->phy_base + PCIE_PHY_CMN_REG4); - /* Assert RX_EQS and RX_EQS_SEL */ - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL - | PCIE_PHY_CMN_REG24_RX_EQ, - imx_pcie->phy_base + PCIE_PHY_CMN_REG24); - /* Assert ATT_MODE */ - writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx_pcie->phy_base + PCIE_PHY_CMN_REG26); - } else { - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); - } - - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); - break; - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, 0); - - usleep_range(200, 500); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, false); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) { @@ -1447,6 +1448,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6q_pcie_core_reset, }, [IMX6SX] = { .variant = IMX6SX, @@ -1462,6 +1464,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, .set_ref_clk = imx6sx_pcie_set_ref_clk, + .core_reset = imx6sx_pcie_core_reset, }, [IMX6QP] = { .variant = IMX6QP, @@ -1478,6 +1481,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6qp_pcie_core_reset, }, [IMX7D] = { .variant = IMX7D, @@ -1491,6 +1495,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, .set_ref_clk = imx7d_pcie_set_ref_clk, + .core_reset = imx7d_pcie_core_reset, }, [IMX8MQ] = { .variant = IMX8MQ,