From patchwork Tue Apr 9 10:13:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13622148 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32E0B12DD9A; Tue, 9 Apr 2024 10:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712657638; cv=none; b=glkgLRoPsDLHMuQb574gcZpEkhyKDzaW+v0jSq8RayRyOIrTyGKS4lIaCmgd5Gave0bj7wtDqux/CAdqbdNv2M3w+4RAkkxA1GH9MbVHaecVT/ixkWHI+WtugOZHi8JL78Nd/3YUDmuWfluu6XfG7ng3A8GzXrFOmyB2ky5cwwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712657638; c=relaxed/simple; bh=V+31wpy+ViuFYyPXxxni0lbwtREaNbHVwxOi2HByI6I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=A5vb06UOuBCgJO40Q4wW94JaCfatQ/Azeb9lj0NNDqofb+WnDhJZL2ZLMB/5hnpFWpyl+Q+AjEzIYQLpuUBzsJCIfYkdpXFZYjMTZibtmSCbpjYqyqvN5tzQ4QW+AWttjazAE9gB4zao3B+OmWofDYxObLfzwCKXO8OCMkrmVVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=k2AwWlKS; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="k2AwWlKS" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4399e65b028862; Tue, 9 Apr 2024 10:13:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=Lge6OIRDCgkl4zCRo6LWVugfANWljw5EKDyEYyAefvo =; b=k2AwWlKSQz+hnJ8gtFvvrKSSgYxVhEtEk2/8/stm+xbC9DnqHM3gvltVtO1 CMvdfRGIg6KZoGffU7lwvIDivBpzayZY5YFPOokYy0K8Ao6CrkWshaUHIsLEOWpp pNVv8mV9YYehFZh1CsCbr7sI/fRASwcoilb39d36+9+VSIfNuOc+U67wHb2uEBy8 O9rWlCEZxZ3Ga83Pe7UazwWVxp9H8tsmWYUFpl++7QMvgLodyRhULzT6+ggXo/26 FGVLLnsyDB+GSYREl6+fmkhgfZTZO2y3zeREgBiSp7mnuh1GhRa3XRktoVdur6s1 4yZd21vBm/Q8t9Y4Yi0x7U9xqHg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xcvtk0r1p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Apr 2024 10:13:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 439ADgY0026773 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 Apr 2024 10:13:42 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 9 Apr 2024 03:13:35 -0700 From: Krishna chaitanya chundru Date: Tue, 9 Apr 2024 15:43:19 +0530 Subject: [PATCH v10 1/6] arm64: dts: qcom: sm8450: Add interconnect path to PCIe node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240409-opp_support-v10-1-1956e6be343f@quicinc.com> References: <20240409-opp_support-v10-0-1956e6be343f@quicinc.com> In-Reply-To: <20240409-opp_support-v10-0-1956e6be343f@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1712657607; l=1661; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=V+31wpy+ViuFYyPXxxni0lbwtREaNbHVwxOi2HByI6I=; b=HhwUyucsY/xTG7xcwjO3qg7WlJIC7Bu01VgxgAv+SHx9M3rzfMO60+By2uo2OQp2v51pWomeK yjpT0BF17MoDvBH/ftI7Eg1qEsRB2Vu3UwEJKLR4iZA8mULeH38bFDq X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QTCtU-YOlL9WPKYXISqfq-LiCfDoRz7o X-Proofpoint-ORIG-GUID: QTCtU-YOlL9WPKYXISqfq-LiCfDoRz7o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-09_06,2024-04-05_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404090065 Add PCIe-MEM & CPU-PCIe interconnect path to the PCIe nodes. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..615296e13c43 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1807,6 +1807,12 @@ pcie0: pcie@1c00000 { <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1930,6 +1936,12 @@ pcie1: pcie@1c08000 { <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>,