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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?RVoaRrO9qwc6d2WUT6NbodZJUQUc?= =?utf-8?q?+mmLil6iP3meIzPKQgXT46/f44roxmQCjF0+ohbrEHrbn73naNBr8kdzN73HYw3L1?= =?utf-8?q?rmc7cKhwcQmks1PiQg7jw4AuBCYo2t3b5pkfzzC0P3cDbUN5SfhtMuOpMit/5DTct?= =?utf-8?q?lU3yEwHI1w5/oEwoOePOoP62XL2WglWFKGz7xjQIgNNcdOPhYuHmfxoyETBmpHL+8?= =?utf-8?q?jnlyadYAy45/i6LIbaQ43MdJWylGH7U61nPXYLJfjr9EKC0Cn293GidfABuaSoLJM?= =?utf-8?q?thVLF3k+oauTDQNgk1ezs72eeGMI6tOEXtaFlFl9JDwTzETpuTtxNpN+/zuIGY+YG?= =?utf-8?q?Y2TsYUkJk+M1nJmRdRBTFQ344BhzeiLY/ka582zqQUKyBiu7Gw4FTPK0hoCKFnwqe?= =?utf-8?q?Mg2cjMKWGZKlpgLvzgiZ0noyuVEZhFoybhajs/ukTbMk6d/oZVNMs/SjG3mAGFe6y?= =?utf-8?q?PqOnOgVXXYS8uQbiSu07+uBpUvNbGWaubzLO9MXS02mc1mwSEA9ewkQjzVlhmQNvB?= =?utf-8?q?aHHozaSEoMMEPuZfzwNytg3VzeuC5aV5bdHZqf+XxbZ2VbnexZAmqTwXvWQa5cp4D?= =?utf-8?q?pJ0QLrmeYrb4nckJIpWIFx9EJxqbotdoek6fVP7oqt7HHqHaEh3UHV0+uH92Mxz1Y?= =?utf-8?q?Wp1QSqpuUDnPLgHlM7GhBcjm1YcQY1SEZPs4e1D52DAqWeUy2UAltlVi5b+UWVa+T?= =?utf-8?q?8I3I1b7zgeqZo6g2HdizOamU0gb3bGQnDrzTWjsNozn/sKg/2E/JSYBcQCQA5Gk42?= =?utf-8?q?+uz1Pb9mbjyRG0O6i0QX5hMcEh5ZbH5gAhIkK/NbzvLP4AueVsUxmOdupnarPiG7j?= =?utf-8?q?9dNbf1AaUMQz3TNvGE2pXs5V0QdOq/0GTy13NBqMoMOU8CJG9HmtfxMwZbmjq4cag?= =?utf-8?q?QP6NF9vGZEgXcA427GZNrsHxe46Bogtlif4CCQ6Jx7lTXeEOJy3zt0nlqD0obMbC6?= =?utf-8?q?977AYls+5llyTyqpwbBdgA7slKNku+4aKGxdj4kpq5CjLVyw1ah4azqxJ6yl/DIVM?= =?utf-8?q?SG3w8fhNQqVxxCwCdOy7DQM3fA9UaSFn04iqq51i5B/+Ss4czuQpgJEUsEjtQcX3n?= =?utf-8?q?SMh8T5eSReF3xbQBUgv3dkyo/ZZaFv1UyB7CsNUhxtWVzqgoFAdZU8dndVNa+fp1Y?= =?utf-8?q?7V7AtTzdQKUkJOmPl672eAoQpPdxFsmTcZPDH4e45jHWjbT18yOji3UpRxHTHEvh6?= =?utf-8?q?J7lSw/j0LIODy+6XXl1rFInw6V2Lex7rKJMu/kXDmDQuufPqwENtdye+1LWDADFeo?= =?utf-8?q?S2hAexy+MjExRNwnQOCLlfN5XfHEVW6EepYECVuJ+iSiINfT3RxXSfcu+EutLSWrg?= =?utf-8?q?8J9UdpVFkmtUW53Ad3uuIHT9rdmTZbkWtOdIPJ+OrkomTEs+Io5cwt1FzzXouIImf?= =?utf-8?q?5Yao4S2zAG0te/3aMUFAHUjEuKXOd4A3yz3x5slrq0tkR0ORLuE/rIRsT6JOTHLy1?= =?utf-8?q?+0UfC2n5vPdyRgyfyQ2sDo9D9cCrXxrATuq6hlbrDf5O1niZX3LH63ktYJF4S70r8?= =?utf-8?q?1WVJe0HWvH1q?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4bf56f52-e684-4e94-ef21-08dc5effdb05 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2024 17:00:16.4904 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jj4Je8nM5pFBX5ClqWv69yRJya4oGMactUjKm0PItcgvQsXllvAihYG66yyPdgWXmpVIWxPZfFwyXeowF0+ZHA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8080 From: Yoshihiro Shimoda Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering INTx IRQs by iATU in the PCIe endpoint mode in near the future. PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of MsgD. So, this implementation supports the data-less messages only for now. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++-- drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index df2575ec5f44c..ba909fade9db1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, upper_32_bits(atu->pci_addr)); - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; @@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); + val = PCIE_ATU_ENABLE; + if (atu->type == PCIE_ATU_TYPE_MSG) { + /* The data-less messages only for now */ + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; + } + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); /* * Make sure ATU enable takes effect before any subsequent config diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index d21db82e586d5..703b50bc5e0f1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -148,11 +148,13 @@ #define PCIE_ATU_TYPE_IO 0x2 #define PCIE_ATU_TYPE_CFG0 0x4 #define PCIE_ATU_TYPE_CFG1 0x5 +#define PCIE_ATU_TYPE_MSG 0x10 #define PCIE_ATU_TD BIT(8) #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 #define PCIE_ATU_UPPER_BASE 0x00C @@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg { int index; int type; u8 func_no; + u8 code; + u8 routing; u64 cpu_addr; u64 pci_addr; u64 size;