From patchwork Wed May 8 13:13:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658730 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B0616BFC5; Wed, 8 May 2024 13:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174071; cv=none; b=o07dyBSUnTXuQjqNxCpQlz2NEHqx9fK26QqmB4eO18KkE0c/1x9HYUm6sYj0tKKMF79vBTwG4RlRVZ3A1b7RafhSnjPtz4Tvu0sBHbQXxZO0SoGFdW8hgA/Z6k1WnMmjRxCzagQYMdJupAtkxR6ps+pvGZFNrzUUAPICFFWhvNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174071; c=relaxed/simple; bh=zV5QDNN0Jd7t4ZstveDXwSQbOhLYZJYhoixvLN8ii44=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RKgPWSLU20BZBih9AG3fEMYblVWCLIzJNUhZTGVtwe3qwkAJfafX7rGHJjttBMEsb703b2tFKQ6mH/ksVL62JU+gt7J5G+Hu+DzY0evwQu1idYGIxXVKtvqbBRYqcknntX+No/FKhlZmyiN7F95NIMBctWpJ/yFDbsV6T6PAZBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fBFG0Tl2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fBFG0Tl2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15D02C3277B; Wed, 8 May 2024 13:14:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174070; bh=zV5QDNN0Jd7t4ZstveDXwSQbOhLYZJYhoixvLN8ii44=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fBFG0Tl207Es9jMIQMTVUytr1QIkFHM6h5fpRHFiZLDTEwn17nn95dUGLB4FVBiJj S0Cg2Fq2xVM0Brebwubo9Sfjfq+3UkWkfczO6H7tmv0mNtLazZipq6ElfjE7e6XZ56 KkBOyikoSRQJJhIni6czWklduns73hwoxyVAUKiysd4XOoXfs6YWLV6fZ11qbUsDrd AqfyagKXuOAPMDBLW7/IVPsp+qz0t0MTDJunUoy/3oGofk5WbGhP+bxq02gXGLF4kK sJtZ2zQ6FD15eWmJPG+rNLJDww+H7Rz84qtuGQSo3fkNxAHpCAlcRUvVMubt6BQ+sr 8IIkkjyi8FArw== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:43 +0200 Subject: [PATCH v3 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-12-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2324; i=cassel@kernel.org; h=from:subject:message-id; bh=zV5QDNN0Jd7t4ZstveDXwSQbOhLYZJYhoixvLN8ii44=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+o7xZ9f5FrNW2OrMelt6wuWiXvuOZteLcw6furgE X3uALEtHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZjIPSOG/0l38jpr+jcemX+l 2C52Q/VcQfFfVdU9j9fbGz7bXZl6Wo/hr8RBDZ/ajdmrch6yl7KsW6F6z8zx7iK7GQbMxbfTtY6 1cAEA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a device tree node representing PCIe endpoint mode. The controller can either be configured to run in Root Complex or Endpoint node. If a user wants to run the controller in endpoint mode, the user has to disable the pcie3x4 node and enable the pcie3x4_ep node. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5519c1430cb7..09a06e8c43b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -136,6 +136,41 @@ pcie3x4_intc: legacy-interrupt-controller { }; }; + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + }; + pcie3x2: pcie@fe160000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>;