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Wed, 8 May 2024 02:22:15 -0700 From: Jon Hunter To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Thierry Reding , "Niklas Cassel" CC: Vidya Sagar , , , Jon Hunter , "Manikanta Maddireddy" Subject: [PATCH V2] PCI: tegra194: Set EP alignment restriction for inbound ATU Date: Wed, 8 May 2024 10:22:07 +0100 Message-ID: <20240508092207.337063-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|MN0PR12MB6365:EE_ X-MS-Office365-Filtering-Correlation-Id: f060025e-62b8-498d-32cb-08dc6f4064f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|82310400017|376005|36860700004; X-Microsoft-Antispam-Message-Info: 5B1LWvzTppc/Sed9vzAbZMcVF4aAxWBxKbVrouefeP6O6d/hFy3zkz2UL5qyjAjWwFo0eQlWp7TQnhexznNFPZ4gVkCmDmyNvypbZAwcAUH136qMwVlg5LAm/fbJHldvGUaQBkd2YcVxKW5nUow4ttwm3q+9K6fH1VnGhx0NoFoSUgIOCXa2SH2Gtl0UAnGbZNF9hd9Xq+KHQUh9HdxqMpohyo4aGp/Ys/hoqw45xfGWHFAMtCnuoI4D8TSW7ZfFE0+huxc6MJXRKa8WCJfD/4SsSrpEJGfl+/qoXgeXuSFZEkg0jM1QG8fC8LaEfV28s2KoVohzntbNc0V/zEdZs2IbM9ocNaolC/6A0cjRg5Lx8wk4d5L5XLyMd+xGnxKck06DzxeoBp3cdwvtBPoIyW8kotYOhAhx5zPwucsE4dkD0vc6Z6ifphTsIxtfOIZbBp+4VSq9iyjh4I5X4baDNER6Mb6NbFoO7lFKBpp1RZWAyrJnt3fGDwt/jd+ms5xhHqQlXGR3kDddq+QhXzH9gxUlwtM1huOyFJ2egAInO/vWAwGrgmUolguN0daI9aivd+Z2X7Vt89TRiMWBnfmZyXsAYlZ66SUQu/DrJKjjrenGB18Vs/rggjc7YtxIGfMPAz6yQ0PAB8FW8a55hsjcQ6pYtc/is/1A7xEccuhU+53lRTKTCRNcmrZxBTFOXxc5cBhpjSkhAmfphO83e+ZW2PUAumPxsff4PmMK6kG6F7cdlPJ0eG0FqvUuQkLYQ9yF0tWhvuB1pV8NQRfnc1erOpMRH5BW62d8M4BEisKTYNRP8U6CbfCygeUmihacmjRWpQOqopj4mTLc3sey2wKojewfXH89YmUN2aTsIAl3rwwNx7fK5dher4WP4efz4WE7ou0wSnJUaib+IdG3Bqf6TOUxXIo5qdQkMs3ulEWgMvCNi3YC7g1JGlMckIlupa+jtX50p/F7obMbjnFKMNbHK6aSy/53bVWA+4i2YVPZvtdORA1FafM7rCS6ALARRi5CvTptfDJSpTIwUlwfT0VISFqU9pSroNlydTOSaMk5dVRudG8gcAnEdcQpnj3hNU5/vj7R2aWWeHHvCGjb7PahJx4sCNi+XSOs8DpQDqq3ITzerNxKNTB9UgVJu4NC/motAaTWTtVlo5dIGNU0JjWolHxcEv4mnLHOoWhH5vUufydHWGzDzx/je0YlKa0j2ppa72tcTvbghb1OqeQ5dIBnL8yTk7oY6ESEkS1+OV1fPr3PAESWLehe7NpqJugEQibm+QHqAuFpRrHW9gu1GlB/CxcYLd5G7aPpLBzOX3GqcaD5QznNFDN1ic7+f4WfRVSVkDBnXWf3qYOC9fto0llBVGSLTpdI0g8KMUlt3sVXJak= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(82310400017)(376005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2024 09:22:34.0692 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f060025e-62b8-498d-32cb-08dc6f4064f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6365 Tegra194 and Tegra234 PCIe EP controllers have 64K alignment restriction for the inbound ATU. Set the endpoint inbound ATU alignment to 64kB in the Tegra194 PCIe driver. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Suggested-by: Manikanta Maddireddy Signed-off-by: Jon Hunter Reviewed-by: Niklas Cassel --- Changes since V1: Updated commit message. drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 93f5433c5c55..4537313ef37a 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2015,6 +2015,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = { .bar[BAR_3] = { .type = BAR_RESERVED, }, .bar[BAR_4] = { .type = BAR_RESERVED, }, .bar[BAR_5] = { .type = BAR_RESERVED, }, + .align = SZ_64K, }; static const struct pci_epc_features*