| Message ID | 20240524092349.158443-1-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: j721e: Add PCIe support for J722S SoC | expand |
Hello, > TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3 > single lane PCIe controller. Add support for the "ti,j722s-pcie-host" > compatible specific to J722S SoC. Applied to controller/j721e, thank you! [01/01] PCI: j721e: Add PCIe support for J722S SoC https://git.kernel.org/pci/pci/c/08e835268c35 Krzysztof
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 85718246016b..cde6cd77e406 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -344,6 +344,13 @@ static const struct j721e_pcie_data j784s4_pcie_ep_data = { .max_lanes = 4, }; +static const struct j721e_pcie_data j722s_pcie_rc_data = { + .mode = PCI_MODE_RC, + .linkdown_irq_regfield = J7200_LINK_DOWN, + .byte_access_allowed = true, + .max_lanes = 1, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -377,6 +384,10 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,j784s4-pcie-ep", .data = &j784s4_pcie_ep_data, }, + { + .compatible = "ti,j722s-pcie-host", + .data = &j722s_pcie_rc_data, + }, {}, };
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3 single lane PCIe controller. Add support for the "ti,j722s-pcie-host" compatible specific to J722S SoC. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Hello, This patch is based on linux-next tagged next-20240523. The dt-bindings patch for the compatible at: https://lore.kernel.org/r/20240124122936.816142-1-s-vadapalli@ti.com/ has been accepted and merged: https://git.kernel.org/pci/pci/c/01fec70206d4 Regards, Siddharth. drivers/pci/controller/cadence/pci-j721e.c | 11 +++++++++++ 1 file changed, 11 insertions(+)