From patchwork Wed May 29 08:29:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678344 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345C416D9BE; Wed, 29 May 2024 08:30:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971408; cv=none; b=prhEPXWLklTZwtI/WQc/P3LbagF931Pvklo+QzhAdt4WFsM9qC1RHXXQYRiDnM4D519cTIU2K3GV8GB3Be6wMmBsKCeT01iE5z6omXA1wejwShxANT2DMk0tMwWldVZ9oWMrmYbG+iZbjqWIb9bVvRjkKzW1R4H97Kvoajn1fyQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971408; c=relaxed/simple; bh=LO909Qkb49dF2RDbiXWZUtB58HFe23RYE1wbMe1vcLI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Sm12zpm78SlPo/13vptBVmwHCdkUMf+rBGTtw/KuP9wFRP2Uc4366K1DyIoG9NQF2rmxUUU9f+Ns5q8bZao+Y5e5/c+bQHNjjY0Zd/s1GbMo2BfPLd6Tkvv6ZXLTDgn74PbCqncflIDJRWf2H7ZXDztPiVmy+VGaNe6H3bl/gGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cBw9VvBc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cBw9VvBc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1AF23C2BD10; Wed, 29 May 2024 08:30:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971407; bh=LO909Qkb49dF2RDbiXWZUtB58HFe23RYE1wbMe1vcLI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cBw9VvBcV1o5536nQZc+jpLoTRiQB5iWrsAWafOAX/+iRPbfpmCEevODeAijFiVFH is94eFUQkngtapUPj33iBBOa5dG2GDrM1ZYUZhfwcQNC1iNlypwGCDSfba9zyf6v/f VflaC03AdPaIXD5guCFfFF6r4R/lS4SmKBR5K7gDmlAbbFXI0faWNyOlCk5hLjK0ts 2Sz1W2GoYhQ5tDvG7HiV5gNSY+eatigFxHD0dymvuXdWxVR5i15ATFCW2GEGJGxYQH bd+jUUuHvqzy997jyv8GBc5ua68u8vZItG87JMaSd76wVBg5lTeY1HqWmj98LFDaeY JtcVMqaAeAirw== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:07 +0200 Subject: [PATCH v4 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-13-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3452; i=cassel@kernel.org; h=from:subject:message-id; bh=LO909Qkb49dF2RDbiXWZUtB58HFe23RYE1wbMe1vcLI=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoc2R3GI9XocrK5x5whJLLWw3H6w5YDYHdaFQpxun 56EfJvWUcrCIMbFICumyOL7w2V/cbf7lOOKd2xg5rAygQxh4OIUgIm4ljEybMjbMmMnU1Hikoyu dfqWC2K+fnv3mn8uVwKTp4Og13cZc0aGX7pr+0xiU+/LxKzf6pSs/m/RX28+Dln7dr+yfw6L+K7 zAgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add rock5b overlays for PCIe endpoint mode support. If using the rock5b as an endpoint against a normal PC, only the rk3588-rock-5b-pcie-ep.dtbo needs to be applied. If using two rock5b:s, with one board as EP and the other board as RC, rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to be applied to the respective boards. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f42fa62b4064..df7f5103b018 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb @@ -134,3 +136,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_rk3588-rock-5b += -@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +};