From patchwork Fri May 31 08:53:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13681326 X-Patchwork-Delegate: kw@linux.com Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449B215575A; Fri, 31 May 2024 08:54:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717145664; cv=none; b=oqMx1djMiHcdYYB0sm7VgqG3CGSHJpX/tDl8gARary9QxXy7ptURfLBWfRx2/U9tpgpM7Hk6l9ExwdUK2pVIJw3VnnGDZ6WIN66oSLShJtgDFpgyejUKIJIp9qyurXnqTCQNyXlQpB8rKqLFOvUylqs57QRNgg4HIlYlikYjif8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717145664; c=relaxed/simple; bh=Oo6bxxOy97R0LewTp0VK1yx3l148GkL3pKqSia9JUdA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g+GpnnSQb9k/tp9tHrH+s25+RgE6fK9f6HqX68rF1mR7lKutEro6+ENG4GbkIGM4vJYTUOPhPREDsIEopUE3xSSvAtTWg4N/yHpmUbeI/sVqazj9Eg3ZjHDBR3yNLX4/HzouhTIKa7fkwyBEV9KeVRLDeMFtxcQ0xhmTTyx6dOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=FombdEQO; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="FombdEQO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1717145662; x=1748681662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Oo6bxxOy97R0LewTp0VK1yx3l148GkL3pKqSia9JUdA=; b=FombdEQOWgr36mzF8T/rdRy2ZoNUyYYxgGGq2g1xCYc2KCvmP9dhW7/w kZIrqEr9QWOHr86KfDTL/h5xjcBw0pc+SGSWoNd/O5qlTkScvxSYgH8oL lnOyblJLrE/lfrrzNv2St2gKdyOlpJjGsrdE58C1t/7qxNw2UP8XDleHs CtsaTbZz2/3BW5WylcTfhD3a46afrt3M3LjFudCpM8sBOc1/Uv2aUHs0g aBbnEPcLOKOwNaM9loB1zgYRgSCRPE1pxC18UFjOZJVdvEZirjzHW60ao JlL27FpnVm7+GXJufemQXobgXyh+O0U5c7gyamQl8uetOui8sxXdcCK4s w==; X-CSE-ConnectionGUID: l/lpyU7jQm+PQYj0dIm0ag== X-CSE-MsgGUID: qmmgSkVxTHeMUclhTpfFRw== X-IronPort-AV: E=Sophos;i="6.08,203,1712646000"; d="scan'208";a="194194715" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 31 May 2024 01:54:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 31 May 2024 01:54:00 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 31 May 2024 01:53:58 -0700 From: Daire McNamara To: CC: Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , , , Daire McNamara Subject: [PATCH 1/2] PCI: microchip: Fix outbound address translation tables Date: Fri, 31 May 2024 09:53:32 +0100 Message-ID: <20240531085333.2501399-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240531085333.2501399-1-daire.mcnamara@microchip.com> References: <20240531085333.2501399-1-daire.mcnamara@microchip.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara --- drivers/pci/controller/pcie-microchip-host.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..0795cd122a4a 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -983,7 +983,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & 0xffffffff, + pci_addr & 0xffffffff, resource_size(entry->res)); index++; } @@ -1117,8 +1118,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, + cfg->res.start & 0xffffffff, resource_size(&cfg->res)); /* Need some fixups in config space */