From patchwork Fri Jun 7 11:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13689743 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8E7C8287F; Fri, 7 Jun 2024 11:15:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758923; cv=none; b=fmokUbzYPEKEfiJcUQX6Dt/K+qDlK9oym2Y7o0NoGuFfTLSlN4ie9HFb/HwDZJ0UqneKIaVFtSo64mWDRAPXPL3X1WXVc+QN71y0AvGOMc0oZ+hiksjknf2QvPjNOamb6gU7+uuQc6tTlyYv3giqsBDAS2456bUcNu0E/rA8MUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717758923; c=relaxed/simple; bh=doSN4oEHyy0FD60flsg7cFcvOvKVYbDH1myDSVHKy/Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PPc1Ba9qd9kGljJ67WmICjyjFDXyh4jiIitL3pBMjyfgJioowdCPMohhbwJ133tAenIbd/MSFyJpzeeLE4+5XTAeV3bNUoOI3wsEFPOJHEC04aMkTCDfHmwtl8AqCWWaMSmyHTSPuexfvxsQBNrRtczUEZX8yD3nLiCyKAaKK1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z2S+Apsr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z2S+Apsr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 98DC6C2BBFC; Fri, 7 Jun 2024 11:15:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758922; bh=doSN4oEHyy0FD60flsg7cFcvOvKVYbDH1myDSVHKy/Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Z2S+ApsrrRlRsaUAIcIkTpZa8MtvQF0yr3MeB9LiCvDACWts4+m8J0ZG6Wi3xxnnr Roz44/gvUAV35bFlNK6GSZPcoR2P8vLeHsddRaE4/gCD5GcVTIseR3wwWISCH7F146 JVQuB60TJ+s/CqX2xtmU6rXcYymFQ6gKryiRsHtNL6TMHJeapSXx01KPLIDmfq10lA T+PmMt3BLRXKfNjQyqNbL2D26011CjL/nAxjS6Th9fDV8yVEIfynAVFbkDwJji3gCO nI78H/YXr0CnDSAETKmiLdtRetCs1lW5yYjVPImC483l+k6Klu6Rm+xxZ3Hx0etY8q fBb3qogJQsceQ== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:32 +0200 Subject: [PATCH v5 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-12-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2395; i=cassel@kernel.org; h=from:subject:message-id; bh=doSN4oEHyy0FD60flsg7cFcvOvKVYbDH1myDSVHKy/Q=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk8qt/qs2J+0oOnmNKuWjML8vzc4a//ZdTg3TpZdN K3k58vHHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZhI+2dGhh9pB88dmyDkvSW8 64fo/iUJJ/R+debteZ8rf9rrhnum2F6G/7GM3au23v5/su3fXeW9eSoWOxflJRvHn+jh3vesVfF IAQMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a device tree node representing PCIe endpoint mode. The controller can either be configured to run in Root Complex or Endpoint node. If a user wants to run the controller in endpoint mode, the user has to disable the pcie3x4 node and enable the pcie3x4_ep node. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5984016b5f96..a88f5a9b6d66 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -186,6 +186,41 @@ pcie3x4_intc: legacy-interrupt-controller { }; }; + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + }; + pcie3x2: pcie@fe160000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>;