| Message ID | 20240609-opp_support-v14-1-801cff862b5a@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: qcom: Add support for OPP | expand |
On Sun, 9 Jun 2024, Krishna chaitanya chundru wrote: > To access the host controller registers of the host controller and the > endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should > be voted otherwise it may lead to NoC (Network on chip) timeout. > We are surviving because of other driver voting for this path. > > As there is less access on this path compared to PCIe to mem path > add minimum vote i.e 1KBps bandwidth always which is sufficient enough > to keep the path active and is recommended by HW team. > > During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while > disabling the boot CPU). So do not disable the CPU-PCIe interconnect path > during S2RAM as that may lead to NoC error. > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 45 +++++++++++++++++++++++++++++++--- > 1 file changed, 41 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 5f9f0ff19baa..ff1d891c8b9a 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -253,6 +253,7 @@ struct qcom_pcie { > struct phy *phy; > struct gpio_desc *reset; > struct icc_path *icc_mem; > + struct icc_path *icc_cpu; > const struct qcom_pcie_cfg *cfg; > struct dentry *debugfs; > bool suspended; > @@ -1369,6 +1370,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) > if (IS_ERR(pcie->icc_mem)) > return PTR_ERR(pcie->icc_mem); > > + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); > + if (IS_ERR(pcie->icc_cpu)) > + return PTR_ERR(pcie->icc_cpu); > /* > * Some Qualcomm platforms require interconnect bandwidth constraints > * to be set before enabling interconnect clocks. > @@ -1378,11 +1382,25 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) > */ > ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); > if (ret) { > - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", > + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", > ret); I think it would be better to separate these message clarifications into a separate patch. It would make both patches more into the point. Other than that, the change looked okay to me.
On Fri, Jun 14, 2024 at 03:14:10PM +0300, Ilpo Järvinen wrote: > On Sun, 9 Jun 2024, Krishna chaitanya chundru wrote: > > > To access the host controller registers of the host controller and the > > endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should > > be voted otherwise it may lead to NoC (Network on chip) timeout. > > We are surviving because of other driver voting for this path. > > > > As there is less access on this path compared to PCIe to mem path > > add minimum vote i.e 1KBps bandwidth always which is sufficient enough > > to keep the path active and is recommended by HW team. > > > > During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while > > disabling the boot CPU). So do not disable the CPU-PCIe interconnect path > > during S2RAM as that may lead to NoC error. > > > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > drivers/pci/controller/dwc/pcie-qcom.c | 45 +++++++++++++++++++++++++++++++--- > > 1 file changed, 41 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > > index 5f9f0ff19baa..ff1d891c8b9a 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > @@ -253,6 +253,7 @@ struct qcom_pcie { > > struct phy *phy; > > struct gpio_desc *reset; > > struct icc_path *icc_mem; > > + struct icc_path *icc_cpu; > > const struct qcom_pcie_cfg *cfg; > > struct dentry *debugfs; > > bool suspended; > > @@ -1369,6 +1370,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) > > if (IS_ERR(pcie->icc_mem)) > > return PTR_ERR(pcie->icc_mem); > > > > + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); > > + if (IS_ERR(pcie->icc_cpu)) > > + return PTR_ERR(pcie->icc_cpu); > > /* > > * Some Qualcomm platforms require interconnect bandwidth constraints > > * to be set before enabling interconnect clocks. > > @@ -1378,11 +1382,25 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) > > */ > > ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); > > if (ret) { > > - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", > > + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", > > ret); > > I think it would be better to separate these message clarifications into a > separate patch. It would make both patches more into the point. > No, it doesn't make sense. This patch introduces ICC vote for CPU-PCIe path, so it _should_ also update the error message. - Mani > Other than that, the change looked okay to me. > > -- > i. > > > return ret; > > } > > > > + /* > > + * Since the CPU-PCIe path is only used for activities like register > > + * access of the host controller and endpoint Config/BAR space access, > > + * HW team has recommended to use a minimal bandwidth of 1KBps just to > > + * keep the path active. > > + */ > > + ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); > > + if (ret) { > > + dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", > > + ret); > > + icc_set_bw(pcie->icc_mem, 0, 0); > > + return ret; > > + } > > + > > return 0; > > } > > > > @@ -1408,7 +1426,7 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) > > > > ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); > > if (ret) { > > - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", > > + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", > > ret); > > } > > } > > @@ -1570,7 +1588,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) > > */ > > ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); > > if (ret) { > > - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); > > + dev_err(dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); > > return ret; > > } > > > > @@ -1594,7 +1612,18 @@ static int qcom_pcie_suspend_noirq(struct device *dev) > > pcie->suspended = true; > > } > > > > - return 0; > > + /* > > + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. > > + * Because on some platforms, DBI access can happen very late during the > > + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC > > + * error. > > + */ > > + if (pm_suspend_target_state != PM_SUSPEND_MEM) { > > + ret = icc_disable(pcie->icc_cpu); > > + if (ret) > > + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); > > + } > > + return ret; > > } > > > > static int qcom_pcie_resume_noirq(struct device *dev) > > @@ -1602,6 +1631,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) > > struct qcom_pcie *pcie = dev_get_drvdata(dev); > > int ret; > > > > + if (pm_suspend_target_state != PM_SUSPEND_MEM) { > > + ret = icc_enable(pcie->icc_cpu); > > + if (ret) { > > + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); > > + return ret; > > + } > > + } > > + > > if (pcie->suspended) { > > ret = qcom_pcie_host_init(&pcie->pci->pp); > > if (ret) > > > >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5f9f0ff19baa..ff1d891c8b9a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -253,6 +253,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; + struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; @@ -1369,6 +1370,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) if (IS_ERR(pcie->icc_mem)) return PTR_ERR(pcie->icc_mem); + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); + if (IS_ERR(pcie->icc_cpu)) + return PTR_ERR(pcie->icc_cpu); /* * Some Qualcomm platforms require interconnect bandwidth constraints * to be set before enabling interconnect clocks. @@ -1378,11 +1382,25 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) */ ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); return ret; } + /* + * Since the CPU-PCIe path is only used for activities like register + * access of the host controller and endpoint Config/BAR space access, + * HW team has recommended to use a minimal bandwidth of 1KBps just to + * keep the path active. + */ + ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); + if (ret) { + dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", + ret); + icc_set_bw(pcie->icc_mem, 0, 0); + return ret; + } + return 0; } @@ -1408,7 +1426,7 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); } } @@ -1570,7 +1588,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) */ ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); if (ret) { - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); + dev_err(dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); return ret; } @@ -1594,7 +1612,18 @@ static int qcom_pcie_suspend_noirq(struct device *dev) pcie->suspended = true; } - return 0; + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_disable(pcie->icc_cpu); + if (ret) + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); + } + return ret; } static int qcom_pcie_resume_noirq(struct device *dev) @@ -1602,6 +1631,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); int ret; + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); + return ret; + } + } + if (pcie->suspended) { ret = qcom_pcie_host_init(&pcie->pci->pp); if (ret)