Message ID | 20240621112915.3434402-4-daire.mcnamara@microchip.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Krzysztof WilczyĆski |
Headers | show |
Series | Fix address translations on MPFS PCIe controller | expand |
On Fri, 21 Jun 2024 12:29:15 +0100, daire.mcnamara@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > PolarFire SoC may be configured in a way that requires non-coherent DMA > handling. On RISC-V, buses are coherent by default & the dma-noncoherent > property is required to denote buses or devices that are non-coherent. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > --- > Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..c84e1ae20532 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -52,6 +52,8 @@ properties: items: pattern: '^fic[0-3]$' + dma-noncoherent: true + interrupts: minItems: 1 items: