From patchwork Fri Jun 21 11:29:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13707311 X-Patchwork-Delegate: kw@linux.com Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11C40174EC2; Fri, 21 Jun 2024 11:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969405; cv=none; b=MEOg7QZjsYLnv2hfy9dJ5shMTnDtBqLY6cprl1gk+xiSLgFzdRA5WEBAPRe6/CyanJqVCOGPuZBsPB6CXO6EdJOecNvj05y/GS5NDJnghaAEhH8Hk6uMiH0Ick6IFjqrXlz6oGTMoLuf+W7LmNB7Y8Etc9KaNkXtqRg3jUPotu4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718969405; c=relaxed/simple; bh=eOM+rlNe4Ccmiqqj78VRC7CbyAJhediEgq9+gqUJt5c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kDiRTkI40vB4Swy4WZcma/JTsC/kQf17Kqu5KJJ532D5mvqiRn8U8HQojyZ8OPgU8bTwDIV3e/7kdHFqQ+1oN4+CuzEcaXTMhHnh37JW8x6pgTl0LNP0Gow83FhbfL/EcNrmq84Qab0rwvlqh/H+zTE9o0uJmrXbn1ffGE/PmpY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=BdZhAPw3; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="BdZhAPw3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718969404; x=1750505404; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eOM+rlNe4Ccmiqqj78VRC7CbyAJhediEgq9+gqUJt5c=; b=BdZhAPw3wQu9V3Zy94zBjcAjDhLAJUdD9eKdTFjG8zHfdFAa/KJ1EmMl q0ThJ9lM9U6mGcCioVpqZXtv/M+RNA2biDy6X543Z9PkiVUd1sgidphB9 /JCilIkhSlgTmEzvz+o3oHveCJkhCYhzA9pOqLSG3v3ns6nwJ3Z2I0ujt JN0mGoRnDrmBo85AzGLhXvdYvRUeNYn3+d33yZhUUGNlX4YeqKa1ee1TL JCnYso7e7WqDo14c6YxUVMpi0QscwXz3LU3qFmafVBn0SPh2iuiZ46QYN DTT0tNzrK2lPUnIxIXmNO8VCLxP5CqlD+GX/kzVUGKKJXBlLd2wFBHC7W g==; X-CSE-ConnectionGUID: MLVdO+kgSZidOgeJsnHSMg== X-CSE-MsgGUID: dO+OJ/qNSuS3vu3+Mtuk5A== X-IronPort-AV: E=Sophos;i="6.08,254,1712646000"; d="scan'208";a="259209056" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jun 2024 04:30:02 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 21 Jun 2024 04:29:36 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 21 Jun 2024 04:29:33 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v4 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent Date: Fri, 21 Jun 2024 12:29:15 +0100 Message-ID: <20240621112915.3434402-4-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621112915.3434402-1-daire.mcnamara@microchip.com> References: <20240621112915.3434402-1-daire.mcnamara@microchip.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Conor Dooley PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..c84e1ae20532 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -52,6 +52,8 @@ properties: items: pattern: '^fic[0-3]$' + dma-noncoherent: true + interrupts: minItems: 1 items: