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Signed-off-by: Stanimir Varbanov --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 218 ++++++++++++++++++++-- 1 file changed, 202 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index bccb7318ce7e..358b129a0f65 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -186,17 +186,30 @@ cma: linux,cma { }; }; - soc: soc@107c000000 { + soc: soc@0 { compatible = "simple-bus"; - ranges = <0x00000000 0x10 0x00000000 0x80000000>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + + ranges = + <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + dma-ranges = + <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; sdio1: mmc@fff000 { compatible = "brcm,bcm2712-sdhci", "brcm,sdhci-brcmstb"; - reg = <0x00fff000 0x260>, - <0x00fff400 0x200>; + reg = <0x10 0x00fff000 0x0 0x260>, + <0x10 0x00fff400 0x0 0x200>; reg-names = "host", "cfg"; interrupts = ; clocks = <&clk_emmc2>; @@ -206,7 +219,7 @@ sdio1: mmc@fff000 { system_timer: timer@7c003000 { compatible = "brcm,bcm2835-system-timer"; - reg = <0x7c003000 0x1000>; + reg = <0x10 0x7c003000 0x0 0x1000>; interrupts = , , , @@ -216,19 +229,19 @@ system_timer: timer@7c003000 { mailbox: mailbox@7c013880 { compatible = "brcm,bcm2835-mbox"; - reg = <0x7c013880 0x40>; + reg = <0x10 0x7c013880 0x0 0x40>; interrupts = ; #mbox-cells = <0>; }; local_intc: local-intc@7cd00000 { compatible = "brcm,bcm2836-l1-intc"; - reg = <0x7cd00000 0x100>; + reg = <0x10 0x7cd00000 0x0 0x100>; }; uart10: serial@7d001000 { compatible = "arm,pl011", "arm,primecell"; - reg = <0x7d001000 0x200>; + reg = <0x10 0x7d001000 0x0 0x200>; interrupts = ; clocks = <&clk_uart>, <&clk_vpu>; clock-names = "uartclk", "apb_pclk"; @@ -238,7 +251,7 @@ uart10: serial@7d001000 { interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; - reg = <0x7d517000 0x10>; + reg = <0x10 0x7d517000 0x0 0x10>; interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -246,7 +259,7 @@ interrupt-controller@7d517000 { gio_aon: gpio@7d517c00 { compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x7d517c00 0x40>; + reg = <0x10 0x7d517c00 0x0 0x40>; gpio-controller; #gpio-cells = <2>; brcm,gpio-bank-widths = <17 6>; @@ -258,13 +271,186 @@ gio_aon: gpio@7d517c00 { gicv2: interrupt-controller@7fff9000 { compatible = "arm,gic-400"; - reg = <0x7fff9000 0x1000>, - <0x7fffa000 0x2000>, - <0x7fffc000 0x2000>, - <0x7fffe000 0x2000>; + reg = <0x10 0x7fff9000 0x0 0x1000>, + <0x10 0x7fffa000 0x0 0x2000>, + <0x10 0x7fffc000 0x0 0x2000>, + <0x10 0x7fffe000 0x0 0x2000>; interrupt-controller; #interrupt-cells = <3>; }; + + mip0: msi-controller@130000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x10 0x00130000 0x00 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <128>; + brcm,msi-num-spis = <64>; + brcm,msi-offset = <0>; + brcm,msi-pci-addr = <0xff 0xfffff000>; + }; + + mip1: msi-controller@131000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x10 0x00131000 0x00 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <247>; + /* Actually 20 total, but the others are + * both sparse and non-consecutive + */ + brcm,msi-num-spis = <8>; + brcm,msi-offset = <8>; + brcm,msi-pci-addr = <0xff 0xffffe000>; + }; + + pcie_rescal: reset-controller@119500 { + compatible = "brcm,bcm7216-pcie-sata-rescal"; + reg = <0x10 0x00119500 0x00 0x10>; + #reset-cells = <0>; + }; + + bcm_reset: reset-controller@1504318 { + compatible = "brcm,brcmstb-reset"; + reg = <0x10 0x01504318 0x00 0x30>; + #reset-cells = <1>; + }; + + /* Single-lane Gen3 PCIe + * Outbound window at 14_0000_0000-17_ffff_ffff + */ + pcie0: pcie@100000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00100000 0x0 0x9310>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* Unused interrupts: 208: AER, 215: NMI, 216: PME */ + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 42>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&pcie0>; + + ranges = <0x02000000 0x00 0x00000000 + 0x17 0x00000000 + 0x0 0xfffffffc>, + <0x43000000 0x04 0x00000000 + 0x14 0x00000000 + 0x3 0x00000000>; + + dma-ranges = <0x43000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; + + /* Single-lane Gen3 PCIe + * Outbound window at 18_0000_0000-1b_ffff_ffff + */ + pcie1: pcie@110000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00110000 0x0 0x9310>; + device_type = "pci"; + linux,pci-domain = <1>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* Unused interrupts: 218: AER, 225: NMI, 226: PME */ + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 43>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&mip1>; + + ranges = <0x02000000 0x00 0x00000000 + 0x1b 0x00000000 + 0x00 0xfffffffc>, + <0x43000000 0x04 0x00000000 + 0x18 0x00000000 + 0x03 0x00000000>; + + dma-ranges = <0x03000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; + + /* Quad-lane Gen3 PCIe + * Outbound window at 1c_0000_0000-1f_ffff_ffff + */ + pcie2: pcie@120000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00120000 0x00 0x9310>; + device_type = "pci"; + linux,pci-domain = <2>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <4>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* Unused interrupts: 228: AER, 235: NMI, 236: PME */ + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 44>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-parent = <&mip0>; + + // ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 + ranges = <0x02000000 0x00 0x00000000 + 0x1f 0x00000000 + 0x0 0xfffffffc>, + // 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 + <0x43000000 0x04 0x00000000 + 0x1c 0x00000000 + 0x03 0x00000000>; + + // 64GB system RAM space at PCIe 10_0000_0000 + dma-ranges = <0x02000000 0x00 0x00000000 + 0x1f 0x00000000 + 0x00 0x00400000>, + <0x43000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; }; timer {