| Message ID | 20240716092347.2177153-4-quic_srichara@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add PCIe support for IPQ9574 | expand |
On 16.07.2024 11:23 AM, Sricharan R wrote: > From: devi priya <quic_devipriy@quicinc.com> > > Enable the PCIe controller and PHY nodes corresponding to RDP 433. > > Signed-off-by: devi priya <quic_devipriy@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > [V6] No change. > > arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ > 1 file changed, 113 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > index 1bb8d96c9a82..f4b6d540612c 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts > @@ -8,6 +8,7 @@ > > /dts-v1/; > > +#include <dt-bindings/gpio/gpio.h> > #include "ipq9574-rdp-common.dtsi" > > / { > @@ -15,6 +16,45 @@ / { > compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; > }; > > +&pcie1_phy { > + status = "okay"; > +}; > + > +&pcie1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie1_default>; property-n property-names please Konrad
On 7/16/2024 5:33 PM, Konrad Dybcio wrote: > On 16.07.2024 11:23 AM, Sricharan R wrote: >> From: devi priya <quic_devipriy@quicinc.com> >> >> Enable the PCIe controller and PHY nodes corresponding to RDP 433. >> >> Signed-off-by: devi priya <quic_devipriy@quicinc.com> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> [V6] No change. >> >> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ >> 1 file changed, 113 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >> index 1bb8d96c9a82..f4b6d540612c 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >> @@ -8,6 +8,7 @@ >> >> /dts-v1/; >> >> +#include <dt-bindings/gpio/gpio.h> >> #include "ipq9574-rdp-common.dtsi" >> >> / { >> @@ -15,6 +16,45 @@ / { >> compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; >> }; >> >> +&pcie1_phy { >> + status = "okay"; >> +}; >> + >> +&pcie1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pcie1_default>; > property-n > property-names ok, will fix Regards, Sricharan
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 1bb8d96c9a82..f4b6d540612c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "ipq9574-rdp-common.dtsi" / { @@ -15,6 +16,45 @@ / { compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; }; +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default>; + + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default>; + + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie3_phy { + status = "okay"; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_default>; + + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; @@ -28,6 +68,79 @@ &sdhc_1 { }; &tlmm { + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio25"; + function = "pcie1_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio27"; + function = "pcie1_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins = "gpio28"; + function = "pcie2_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio30"; + function = "pcie2_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio31"; + function = "pcie3_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio32"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio33"; + function = "pcie3_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio5";